ITE IT8661F changes to match the common code structure.
- it8661f_enable_serial() is now in the usual format, using pnp_* functions. - Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode(). - Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz. - Factor out it8661f_enable_logical_devices(), might not be needed though. We leave it here until it's confirmed on hardware that it's not needed. - Move some #defines to it8661f.h. - Drop no longer used it8661f_sio_write(). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
c29246739a
commit
f228a6cf93
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@ -23,6 +23,7 @@
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/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
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/* Logical device numbers (LDNs). */
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#define IT8661F_FDC 0x00 /* Floppy */
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#define IT8661F_SP1 0x01 /* Com1 */
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#define IT8661F_SP2 0x02 /* Com2 */
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@ -30,4 +31,25 @@
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#define IT8661F_IR 0x04 /* IR */
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#define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */
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/* Register and bit definitions. */
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#define IT8661F_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8661F_REG_LDE 0x23 /* PnP Logical Device Enable. */
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#define IT8661F_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
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#define IT8661F_ISA_PNP_PORT 0x0279 /* Write-only. */
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#define IT8661F_CLKIN_24_MHZ 0
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#define IT8661F_CLKIN_48_MHZ 1
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/*
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* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data.
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*/
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static const u8 init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
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0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
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};
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#endif
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@ -21,74 +21,59 @@
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#include <arch/romcc_io.h>
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#include "it8661f.h"
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/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
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#define SIO_BASE 0x3f0
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8661F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8661F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
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#define IT8661F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
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#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
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/*
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* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data.
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*/
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static const u8 init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
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0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
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};
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static void it8661f_sio_write(u8 ldn, u8 index, u8 value)
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{
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outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
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outb(ldn, SIO_DATA);
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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/* Enable the serial port(s). */
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static void it8661f_enable_serial(device_t dev, u16 iobase)
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/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
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/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
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/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
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/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
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static void pnp_enter_ext_func_mode(device_t dev)
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{
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int i;
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u16 port = dev >> 8;
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/* (1) Enter the configuration state (MB PnP mode). */
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/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
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/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
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/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
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/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
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outb(0x86, IT8661F_CONFIGURATION_PORT);
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outb(0x80, IT8661F_CONFIGURATION_PORT);
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outb(0x55, IT8661F_CONFIGURATION_PORT);
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outb(0x55, IT8661F_CONFIGURATION_PORT);
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/* TODO: Don't hardcode Super I/O config port to 0x3f0. */
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outb(0x86, IT8661F_ISA_PNP_PORT);
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outb(0x80, IT8661F_ISA_PNP_PORT);
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outb(0x55, IT8661F_ISA_PNP_PORT);
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outb(0x55, IT8661F_ISA_PNP_PORT);
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/* Sequentially write the 32 special values. */
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for (i = 0; i < 32; i++)
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outb(init_values[i], SIO_BASE);
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/* (2) Modify the data of configuration registers. */
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/*
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* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
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* PP (3), IR (4). Bits 5-7 are reserved.
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*/
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
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/* Enable serial port(s). */
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it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */
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it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */
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/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
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(clear bit 0). */
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
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/* (3) Exit the configuration state (MB PnP mode). */
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);
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outb(init_values[i], port);
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}
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static void pnp_exit_ext_func_mode(device_t dev)
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{
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pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
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}
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/*
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* The logical devices will only be involved in the ISA PnP sequence if their
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* respective enable bits in IT8661F_REG_LDE are set.
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*
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* TODO: Find out if we actually need this (we use MB PnP mode).
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*
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* Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
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*/
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static void it8661f_enable_logical_devices(device_t dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
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pnp_exit_ext_func_mode(dev);
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}
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static void it8661f_set_clkin(device_t dev, u8 clkin)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
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pnp_exit_ext_func_mode(dev);
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}
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static void it8661f_enable_serial(device_t dev, u16 iobase)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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pnp_exit_ext_func_mode(dev);
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}
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@ -25,10 +25,12 @@
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#include "chip.h"
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#include "it8661f.h"
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/* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */
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static void init(device_t dev)
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{
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struct superio_ite_it8661f_config *conf = dev->chip_info;
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struct resource *res0, *res1;
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struct resource *res0;
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if (!dev->enabled)
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return;
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