haswell: calibrate 24MHz clock against BCLK
On haswell ULT systems there is a 24MHz clock that continuously runs when deep package c-states are entered. The 100MHz BCLK is shut down in the lower c-states. When the package wakes back up a conversion formula needs to be applied. The 24MHz calibration is done using the internal PCODE unit. Change-Id: I6be7702fb1de1429273724536f5af9125b98da64 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48292 Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4136 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -100,6 +100,25 @@
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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/* PCODE MMIO communications live in the MCHBAR. */
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#define BIOS_MAILBOX_INTERFACE 0x5da4
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#define MAILBOX_RUN_BUSY (1 << 31)
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#define MAILBOX_BIOS_CMD_READ_PCS 1
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#define MAILBOX_BIOS_CMD_WRITE_PCS 2
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#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
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#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
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/* Errors are returned back in bits 7:0. */
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#define MAILBOX_BIOS_ERROR_NONE 0
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#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
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#define MAILBOX_BIOS_ERROR_TIMEOUT 2
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#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
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#define MAILBOX_BIOS_ERROR_RESERVED 4
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#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
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#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
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#define MAILBOX_BIOS_ERROR_VR_ERROR 7
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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@ -34,6 +34,7 @@
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#include <cpu/intel/turbo.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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@ -217,6 +218,62 @@ static int is_ult(void)
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return ult;
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}
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/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
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* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
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* when a core is woken up. */
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static int pcode_ready(void)
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{
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int wait_count;
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const int delay_step = 10;
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wait_count = 0;
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do {
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if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
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return 0;
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wait_count += delay_step;
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udelay(delay_step);
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} while (wait_count < 1000);
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return -1;
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}
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static void calibrate_24mhz_bclk(void)
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{
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int err_code;
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
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return;
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}
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/* A non-zero value initiates the PCODE calibration. */
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MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
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MCHBAR32(BIOS_MAILBOX_INTERFACE) =
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
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return;
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}
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err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
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printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n",
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err_code);
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/* Read the calibrated value. */
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MCHBAR32(BIOS_MAILBOX_INTERFACE) =
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MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
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if (pcode_ready() < 0) {
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printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
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return;
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}
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printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n",
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MCHBAR32(BIOS_MAILBOX_DATA));
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}
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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@ -517,6 +574,9 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
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x86_mtrr_check();
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if (is_ult())
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calibrate_24mhz_bclk();
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/* Call through the cpu driver's initialization. */
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cpu_initialize(0);
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}
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