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nb/intel/i945: Use parallel MP init 

Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.

Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.

This removes the option to disable HT siblings.

Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2018-04-10 15:15:05 +02:00 committed by Patrick Georgi
parent 6336d4c48d
commit f266932836
29 changed files with 22 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/model_106cx/Makefile.inc
View File

@ -2,5 +2,6 @@ ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

12
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@ -85,15 +85,18 @@ static void model_106cx_init(struct device *cpu)
x86_enable_cache();
/* Update the microcode */
intel_update_microcode_from_cbfs();
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */
x86_setup_mtrrs();
x86_mtrr_check();
if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
x86_setup_mtrrs();
x86_mtrr_check();
}
/* Enable the local CPU APICs */
setup_lapic();
@ -110,7 +113,8 @@ static void model_106cx_init(struct device *cpu)
/* TODO: PIC thermal sensor control */
/* Start up my CPU siblings */
intel_sibling_init(cpu);
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_6ex/Makefile.inc
View File

@ -2,5 +2,6 @@ ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
ramstage-y += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin

13
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@ -18,11 +18,8 @@
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@ -118,17 +115,10 @@ static void model_6ex_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
/* Update the microcode */
intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */
x86_setup_mtrrs();
x86_mtrr_check();
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
@ -146,9 +136,6 @@ static void model_6ex_init(struct device *cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
/* Start up my CPU siblings */
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_f3x/Makefile.inc
View File

@ -1,4 +1,5 @@
ramstage-y += model_f3x_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin

5
src/cpu/intel/model_f3x/model_f3x_init.c
View File

@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!intel_ht_sibling()) {
if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
@ -37,7 +37,8 @@ static void model_f3x_init(struct device *cpu)
setup_lapic();
/* Start up my CPU siblings */
intel_sibling_init(cpu);
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_f4x/Makefile.inc
View File

@ -1,4 +1,5 @@
ramstage-y += model_f4x_init.c
subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin

5
src/cpu/intel/model_f4x/model_f4x_init.c
View File

@ -24,7 +24,7 @@ static void model_f4x_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!intel_ht_sibling()) {
if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
@ -37,7 +37,8 @@ static void model_f4x_init(struct device *cpu)
setup_lapic();
/* Start up my CPU siblings */
intel_sibling_init(cpu);
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {

1
src/mainboard/apple/macbook21/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
boot_default=0x40

1
src/mainboard/apple/macbook21/cmos.layout
View File

@ -53,7 +53,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/asus/p5gc-mx/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
gfx_uma_size=8M

1
src/mainboard/asus/p5gc-mx/cmos.layout
View File

@ -31,7 +31,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/getac/p470/cmos.layout
View File

@ -53,7 +53,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
gfx_uma_size=8M

1
src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout
View File

@ -52,7 +52,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/ibase/mb899/cmos.layout
View File

@ -52,7 +52,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/intel/d945gclf/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
gfx_uma_size=8M

1
src/mainboard/intel/d945gclf/cmos.layout
View File

@ -52,7 +52,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/kontron/986lcd-m/cmos.layout
View File

@ -52,7 +52,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/mainboard/lenovo/t60/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
boot_default=0x41

1
src/mainboard/lenovo/t60/cmos.layout
View File

@ -69,7 +69,6 @@ entries
#938 7 r 0 unused
# coreboot config options: cpu
944 1 e 2 hyper_threading
#945 3 r 0 unused
# coreboot config options: ec

1
src/mainboard/lenovo/x60/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
boot_default=0x40

1
src/mainboard/lenovo/x60/cmos.layout
View File

@ -69,7 +69,6 @@ entries
#938 6 r 0 unused
# coreboot config options: cpu
944 1 e 2 hyper_threading
#945 4 r 0 unused
# coreboot config options: ec

1
src/mainboard/lenovo/z61t/cmos.default
View File

@ -1,6 +1,5 @@
boot_option=Fallback
debug_level=Debug
hyper_threading=Enable
nmi=Enable
boot_devices=''
boot_default=0x41

1
src/mainboard/lenovo/z61t/cmos.layout
View File

@ -68,7 +68,6 @@ entries
#938 7 r 0 unused
# coreboot config options: cpu
944 1 e 2 hyper_threading
#945 3 r 0 unused
# coreboot config options: ec

1
src/mainboard/roda/rk886ex/cmos.layout
View File

@ -53,7 +53,6 @@ entries
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge

1
src/northbridge/intel/i945/Kconfig
View File

@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
select PARALLEL_MP
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n

22
src/northbridge/intel/i945/northbridge.c
View File

@ -165,26 +165,6 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, SMRAM, smram);
}
/*
* Really doesn't belong here but will go away with parallel mp init,
* so let it be here for a while...
*/
int cpu_get_apic_id_map(int *apic_id_map)
{
unsigned int i;
/* Logical processors (threads) per core */
const struct cpuid_result cpuid1 = cpuid(1);
/* Read number of cores. */
const char cores = (cpuid1.ebx >> 16) & 0xf;
/* TODO in parallel MP cpuid(1).ebx */
for (i = 0; i < cores; i++)
apic_id_map[i] = i;
return cores;
}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
@ -249,7 +229,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
bsp_init_and_start_aps(dev->link_list);
}
static struct device_operations cpu_bus_ops = {

3
src/southbridge/intel/i82801gx/lpc.c
View File

@ -353,7 +353,8 @@ static void i82801gx_lock_smm(struct device *dev)
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
smm_lock();
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */