nb/intel/nehalem: Remove bogus GT PM init
This was simply copied from sandybridge/gma.c. All these registers read back 0xffffffff or 0 or don't respond to reads. Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35746 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
28bca0546b
commit
f266dc6174
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@ -36,225 +36,6 @@
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#include "chip.h"
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#include "nehalem.h"
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struct gt_powermeter {
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u16 reg;
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u32 value;
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};
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static const struct gt_powermeter snb_pm_gt1[] = {
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{0xa200, 0xcc000000},
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{0xa204, 0x07000040},
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{0xa208, 0x0000fe00},
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{0xa20c, 0x00000000},
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{0xa210, 0x17000000},
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{0xa214, 0x00000021},
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{0xa218, 0x0817fe19},
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{0xa21c, 0x00000000},
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{0xa220, 0x00000000},
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{0xa224, 0xcc000000},
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{0xa228, 0x07000040},
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{0xa22c, 0x0000fe00},
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{0xa230, 0x00000000},
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{0xa234, 0x17000000},
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{0xa238, 0x00000021},
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{0xa23c, 0x0817fe19},
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{0xa240, 0x00000000},
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{0xa244, 0x00000000},
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{0xa248, 0x8000421e},
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{0}
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};
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static const struct gt_powermeter snb_pm_gt2[] = {
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{0xa200, 0x330000a6},
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{0xa204, 0x402d0031},
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{0xa208, 0x00165f83},
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{0xa20c, 0xf1000000},
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{0xa210, 0x00000000},
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{0xa214, 0x00160016},
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{0xa218, 0x002a002b},
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{0xa21c, 0x00000000},
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{0xa220, 0x00000000},
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{0xa224, 0x330000a6},
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{0xa228, 0x402d0031},
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{0xa22c, 0x00165f83},
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{0xa230, 0xf1000000},
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{0xa234, 0x00000000},
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{0xa238, 0x00160016},
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{0xa23c, 0x002a002b},
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{0xa240, 0x00000000},
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{0xa244, 0x00000000},
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{0xa248, 0x8000421e},
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{0}
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};
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static const struct gt_powermeter ivb_pm_gt1[] = {
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{0xa800, 0x00000000},
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{0xa804, 0x00021c00},
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{0xa808, 0x00000403},
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{0xa80c, 0x02001700},
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{0xa810, 0x05000200},
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{0xa814, 0x00000000},
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{0xa818, 0x00690500},
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{0xa81c, 0x0000007f},
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{0xa820, 0x01002501},
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{0xa824, 0x00000300},
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{0xa828, 0x01000331},
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{0xa82c, 0x0000000c},
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{0xa830, 0x00010016},
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{0xa834, 0x01100101},
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{0xa838, 0x00010103},
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{0xa83c, 0x00041300},
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{0xa840, 0x00000b30},
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{0xa844, 0x00000000},
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{0xa848, 0x7f000000},
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{0xa84c, 0x05000008},
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{0xa850, 0x00000001},
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{0xa854, 0x00000004},
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{0xa858, 0x00000007},
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{0xa85c, 0x00000000},
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{0xa860, 0x00010000},
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{0xa248, 0x0000221e},
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{0xa900, 0x00000000},
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{0xa904, 0x00001c00},
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{0xa908, 0x00000000},
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{0xa90c, 0x06000000},
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{0xa910, 0x09000200},
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{0xa914, 0x00000000},
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{0xa918, 0x00590000},
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{0xa91c, 0x00000000},
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{0xa920, 0x04002501},
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{0xa924, 0x00000100},
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{0xa928, 0x03000410},
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{0xa92c, 0x00000000},
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{0xa930, 0x00020000},
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{0xa934, 0x02070106},
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{0xa938, 0x00010100},
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{0xa93c, 0x00401c00},
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{0xa940, 0x00000000},
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{0xa944, 0x00000000},
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{0xa948, 0x10000e00},
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{0xa94c, 0x02000004},
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{0xa950, 0x00000001},
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{0xa954, 0x00000004},
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{0xa960, 0x00060000},
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{0xaa3c, 0x00001c00},
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{0xaa54, 0x00000004},
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{0xaa60, 0x00060000},
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{0}
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};
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static const struct gt_powermeter ivb_pm_gt2_17w[] = {
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{0xa800, 0x20000000},
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{0xa804, 0x000e3800},
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{0xa808, 0x00000806},
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{0xa80c, 0x0c002f00},
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{0xa810, 0x0c000800},
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{0xa814, 0x00000000},
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{0xa818, 0x00d20d00},
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{0xa81c, 0x000000ff},
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{0xa820, 0x03004b02},
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{0xa824, 0x00000600},
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{0xa828, 0x07000773},
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{0xa82c, 0x00000000},
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{0xa830, 0x00020032},
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{0xa834, 0x1520040d},
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{0xa838, 0x00020105},
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{0xa83c, 0x00083700},
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{0xa840, 0x000016ff},
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{0xa844, 0x00000000},
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{0xa848, 0xff000000},
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{0xa84c, 0x0a000010},
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{0xa850, 0x00000002},
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{0xa854, 0x00000008},
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{0xa858, 0x0000000f},
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{0xa85c, 0x00000000},
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{0xa860, 0x00020000},
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{0xa248, 0x0000221e},
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{0xa900, 0x00000000},
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{0xa904, 0x00003800},
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{0xa908, 0x00000000},
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{0xa90c, 0x0c000000},
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{0xa910, 0x12000800},
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{0xa914, 0x00000000},
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{0xa918, 0x00b20000},
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{0xa91c, 0x00000000},
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{0xa920, 0x08004b02},
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{0xa924, 0x00000300},
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{0xa928, 0x01000820},
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{0xa92c, 0x00000000},
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{0xa930, 0x00030000},
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{0xa934, 0x15150406},
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{0xa938, 0x00020300},
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{0xa93c, 0x00903900},
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{0xa940, 0x00000000},
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{0xa944, 0x00000000},
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{0xa948, 0x20001b00},
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{0xa94c, 0x0a000010},
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{0xa950, 0x00000000},
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{0xa954, 0x00000008},
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{0xa960, 0x00110000},
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{0xaa3c, 0x00003900},
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{0xaa54, 0x00000008},
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{0xaa60, 0x00110000},
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{0}
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};
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static const struct gt_powermeter ivb_pm_gt2_35w[] = {
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{0xa800, 0x00000000},
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{0xa804, 0x00030400},
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{0xa808, 0x00000806},
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{0xa80c, 0x0c002f00},
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{0xa810, 0x0c000300},
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{0xa814, 0x00000000},
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{0xa818, 0x00d20d00},
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{0xa81c, 0x000000ff},
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{0xa820, 0x03004b02},
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{0xa824, 0x00000600},
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{0xa828, 0x07000773},
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{0xa82c, 0x00000000},
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{0xa830, 0x00020032},
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{0xa834, 0x1520040d},
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{0xa838, 0x00020105},
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{0xa83c, 0x00083700},
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{0xa840, 0x000016ff},
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{0xa844, 0x00000000},
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{0xa848, 0xff000000},
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{0xa84c, 0x0a000010},
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{0xa850, 0x00000001},
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{0xa854, 0x00000008},
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{0xa858, 0x00000008},
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{0xa85c, 0x00000000},
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{0xa860, 0x00020000},
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{0xa248, 0x0000221e},
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{0xa900, 0x00000000},
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{0xa904, 0x00003800},
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{0xa908, 0x00000000},
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{0xa90c, 0x0c000000},
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{0xa910, 0x12000800},
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{0xa914, 0x00000000},
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{0xa918, 0x00b20000},
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{0xa91c, 0x00000000},
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{0xa920, 0x08004b02},
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{0xa924, 0x00000300},
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{0xa928, 0x01000820},
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{0xa92c, 0x00000000},
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{0xa930, 0x00030000},
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{0xa934, 0x15150406},
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{0xa938, 0x00020300},
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{0xa93c, 0x00903900},
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{0xa940, 0x00000000},
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{0xa944, 0x00000000},
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{0xa948, 0x20001b00},
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{0xa94c, 0x0a000010},
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{0xa950, 0x00000000},
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{0xa954, 0x00000008},
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{0xa960, 0x00110000},
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{0xaa3c, 0x00003900},
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{0xaa54, 0x00000008},
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{0xaa60, 0x00110000},
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{0}
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};
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/* some vga option roms are used for several chipsets but they only have one
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* PCI ID in their header. If we encounter such an option rom, we need to do
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* the mapping ourselves
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@ -281,12 +62,6 @@ void gtt_write(u32 reg, u32 data)
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write32(res2mmio(gtt_res, reg, 0), data);
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}
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static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
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{
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for (; pm && pm->reg; pm++)
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gtt_write(pm->reg, pm->value);
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}
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#define GTT_RETRY 1000
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int gtt_poll(u32 reg, u32 mask, u32 value)
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{
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@ -317,196 +92,6 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
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gnvs_ptr->aslb = aslb;
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}
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static void gma_pm_init_pre_vbios(struct device *dev)
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{
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u32 reg32;
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printk(BIOS_DEBUG, "GT Power Management Init\n");
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gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!gtt_res || !gtt_res->base)
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return;
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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/* 1: Enable force wake */
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gtt_write(0xa18c, 0x00000001);
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gtt_poll(0x130090, (1 << 0), (1 << 0));
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} else {
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gtt_write(0xa180, 1 << 5);
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gtt_write(0xa188, 0xffff0001);
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gtt_poll(0x130040, (1 << 0), (1 << 0));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
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reg32 = gtt_read(0x42004);
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reg32 |= (1 << 14) | (1 << 15);
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gtt_write(0x42004, reg32);
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}
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if (bridge_silicon_revision() >= IVB_STEP_A0) {
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/* Display Reset Acknowledge Settings */
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reg32 = gtt_read(0x45010);
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reg32 |= (1 << 1) | (1 << 0);
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gtt_write(0x45010, reg32);
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}
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/* 2: Get GT SKU from GTT+0x911c[13] */
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reg32 = gtt_read(0x911c);
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (reg32 & (1 << 13)) {
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printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
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gtt_write_powermeter(snb_pm_gt1);
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} else {
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printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n");
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gtt_write_powermeter(snb_pm_gt2);
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}
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} else {
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u32 unit = MCHBAR32(0x5938) & 0xf;
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if (reg32 & (1 << 13)) {
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/* GT1 SKU */
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printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n");
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gtt_write_powermeter(ivb_pm_gt1);
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} else {
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/* GT2 SKU */
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u32 tdp = MCHBAR32(0x5930) & 0x7fff;
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tdp /= (1 << unit);
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if (tdp <= 17) {
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/* <=17W ULV */
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printk(BIOS_DEBUG, "IVB GT2 17W "
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"Power Meter Weights\n");
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gtt_write_powermeter(ivb_pm_gt2_17w);
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} else if ((tdp >= 25) && (tdp <= 35)) {
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/* 25W-35W */
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printk(BIOS_DEBUG, "IVB GT2 25W-35W "
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"Power Meter Weights\n");
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gtt_write_powermeter(ivb_pm_gt2_35w);
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} else {
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/* All others */
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printk(BIOS_DEBUG, "IVB GT2 35W "
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"Power Meter Weights\n");
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gtt_write_powermeter(ivb_pm_gt2_35w);
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}
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}
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}
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/* 3: Gear ratio map */
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gtt_write(0xa004, 0x00000010);
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/* 4: GFXPAUSE */
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gtt_write(0xa000, 0x00070020);
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/* 5: Dynamic EU trip control */
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gtt_write(0xa080, 0x00000004);
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/* 6: ECO bits */
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reg32 = gtt_read(0xa180);
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reg32 |= (1 << 26) | (1 << 31);
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/* (bit 20=1 for SNB step D1+ / IVB A0+) */
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if (bridge_silicon_revision() >= SNB_STEP_D1)
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reg32 |= (1 << 20);
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gtt_write(0xa180, reg32);
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/* 6a: for SnB step D2+ only */
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if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
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(bridge_silicon_revision() >= SNB_STEP_D2)) {
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reg32 = gtt_read(0x9400);
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reg32 |= (1 << 7);
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gtt_write(0x9400, reg32);
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reg32 = gtt_read(0x941c);
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reg32 &= 0xf;
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reg32 |= (1 << 1);
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gtt_write(0x941c, reg32);
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gtt_poll(0x941c, (1 << 1), (0 << 1));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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reg32 = gtt_read(0x907c);
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reg32 |= (1 << 16);
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gtt_write(0x907c, reg32);
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/* 6b: Clocking reset controls */
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gtt_write(0x9424, 0x00000001);
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} else {
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/* 6b: Clocking reset controls */
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gtt_write(0x9424, 0x00000000);
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}
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/* 7 */
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if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
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gtt_write(0x138128, 0x00000029); /* Mailbox Data */
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gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
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if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
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gtt_write(0x138124, 0x8000000a);
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gtt_poll(0x138124, (1 << 31), (0 << 31));
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}
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/* 8 */
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gtt_write(0xa090, 0x00000000); /* RC Control */
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gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
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gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
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gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
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gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
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gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
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/* 9 */
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gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
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gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */
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gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */
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/* 10 */
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gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
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gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
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gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
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gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
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gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
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/* 11 */
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gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
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gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
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gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
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gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
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gtt_write(0xa068, 0x000186a0); /* RP Up EI */
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gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
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gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
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/* 11a: Enable Render Standby (RC6) */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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/*
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* IvyBridge should also support DeepRenderStandby.
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*
|
||||
* Unfortunately it does not work reliably on all SKUs so
|
||||
* disable it here and it can be enabled by the kernel.
|
||||
*/
|
||||
gtt_write(0xa090, 0x88040000); /* HW RC Control */
|
||||
} else {
|
||||
gtt_write(0xa090, 0x88040000); /* HW RC Control */
|
||||
}
|
||||
|
||||
/* 12: Normal Frequency Request */
|
||||
/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */
|
||||
/* only the lower 7 bits are used and shifted left by 25 */
|
||||
reg32 = MCHBAR32(0x5998);
|
||||
reg32 >>= 16;
|
||||
reg32 &= 0x7f;
|
||||
reg32 <<= 25;
|
||||
gtt_write(0xa008, reg32);
|
||||
|
||||
/* 13: RP Control */
|
||||
gtt_write(0xa024, 0x00000592);
|
||||
|
||||
/* 14: Enable PM Interrupts */
|
||||
gtt_write(0x4402c, 0x03000076);
|
||||
|
||||
/* Clear 0x6c024 [8:6] */
|
||||
reg32 = gtt_read(0x6c024);
|
||||
reg32 &= ~0x000001c0;
|
||||
gtt_write(0x6c024, reg32);
|
||||
}
|
||||
|
||||
static void gma_pm_init_post_vbios(struct device *dev)
|
||||
{
|
||||
struct northbridge_intel_nehalem_config *conf = dev->chip_info;
|
||||
|
|
@ -514,19 +99,6 @@ static void gma_pm_init_post_vbios(struct device *dev)
|
|||
|
||||
printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
|
||||
|
||||
/* 15: Deassert Force Wake */
|
||||
if (bridge_silicon_revision() < IVB_STEP_C0) {
|
||||
gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
|
||||
gtt_poll(0x130090, (1 << 0), (0 << 0));
|
||||
} else {
|
||||
gtt_write(0xa188, 0x1fffe);
|
||||
if (gtt_poll(0x130040, (1 << 0), (0 << 0)))
|
||||
gtt_write(0xa188, gtt_read(0xa188) | 1);
|
||||
}
|
||||
|
||||
/* 16: SW RC Control */
|
||||
gtt_write(0xa094, 0x00060000);
|
||||
|
||||
/* Setup Digital Port Hotplug */
|
||||
reg32 = gtt_read(0xc4030);
|
||||
if (!reg32) {
|
||||
|
|
@ -600,8 +172,9 @@ static void gma_func0_init(struct device *dev)
|
|||
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
/* Init graphics power management */
|
||||
gma_pm_init_pre_vbios(dev);
|
||||
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (!gtt_res || !gtt_res->base)
|
||||
return;
|
||||
|
||||
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
|
||||
struct northbridge_intel_nehalem_config *conf = dev->chip_info;
|
||||
|
|
|
|||
Loading…
Reference in New Issue