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tegra132: add I2C6 controller to funit library 

BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.

I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.

Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46
Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212671
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8940
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Tom Warren 2014-08-15 12:39:25 -07:00 committed by Patrick Georgi
parent eb0cf2ef07
commit f270eb9775
3 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/nvidia/tegra132/clk_rst.h
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@ -273,7 +273,7 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
u32 spare_reg0; /* _SPARE_REG0, 0x55c */ u32 spare_reg0; /* _SPARE_REG0, 0x55c */
u32 _rsv32[4]; /* 0x560-0x56c */ u32 _rsv32[4]; /* 0x560-0x56c */
u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
u32 _rsv32_1[7]; /* 0x574-58c */ u32 _rsv32_1[7]; /* 0x574-58c */
u32 plldp_base; /* _PLLDP_BASE, 0x590 */ u32 plldp_base; /* _PLLDP_BASE, 0x590 */
u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ u32 plldp_misc; /* _PLLDP_MISC, 0x594 */
u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
@ -296,8 +296,10 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */
u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */
u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */
u32 _rsv33[5]; /* 0x648-658 */
u32 clk_src_i2c6; /* _CLK_SOURCE_I2C6, 0x65c */
}; };
check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); check_member(clk_rst_ctlr, clk_src_i2c6, 0x65C);
#define TEGRA_DEV_L 0 #define TEGRA_DEV_L 0
#define TEGRA_DEV_H 1 #define TEGRA_DEV_H 1

1
src/soc/nvidia/tegra132/funitcfg.c
View File

@ -88,6 +88,7 @@ static const struct funit_cfg_data funit_data[] = {
FUNIT_DATA(I2C2, i2c2, H), FUNIT_DATA(I2C2, i2c2, H),
FUNIT_DATA(I2C3, i2c3, U), FUNIT_DATA(I2C3, i2c3, U),
FUNIT_DATA(I2C5, i2c5, H), FUNIT_DATA(I2C5, i2c5, H),
FUNIT_DATA(I2C6, i2c6, X),
FUNIT_DATA(SDMMC3, sdmmc3, U), FUNIT_DATA(SDMMC3, sdmmc3, U),
FUNIT_DATA(SDMMC4, sdmmc4, L), FUNIT_DATA(SDMMC4, sdmmc4, L),
FUNIT_DATA_USB(USBD, L), FUNIT_DATA_USB(USBD, L),

1
src/soc/nvidia/tegra132/include/soc/funitcfg.h
View File

@ -33,6 +33,7 @@ enum {
FUNIT_INDEX(I2C2), FUNIT_INDEX(I2C2),
FUNIT_INDEX(I2C3), FUNIT_INDEX(I2C3),
FUNIT_INDEX(I2C5), FUNIT_INDEX(I2C5),
FUNIT_INDEX(I2C6),
FUNIT_INDEX(SDMMC3), FUNIT_INDEX(SDMMC3),
FUNIT_INDEX(SDMMC4), FUNIT_INDEX(SDMMC4),
FUNIT_INDEX(USBD), FUNIT_INDEX(USBD),