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nb/intel/haswell/finalize.c: Align with Broadwell 

Reorder register writes to match the locking order in Broadwell.

Tested on Asrock B85M Pro4, still boots and registers are still locked.

Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 11:07:41 +02:00
parent 6fe3c06614
commit f27662f5ba
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/haswell/finalize.c
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@ -22,12 +22,12 @@ void intel_northbridge_haswell_finalize_smm(void)
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
MCHBAR32_OR(REQLIM, 1UL << 31);
MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31);
MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(CRDTLCK, 1 << 0);
MCHBAR32_OR(MCARBLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0);
MCHBAR32_OR(REQLIM, 1UL << 31);
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
/* Read+write the following */ /* Read+write the following */
MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM);