hp/abm: Switch away from AGESA_LEGACY
Change-Id: Ie2f1eb5a101b9c392a7bd5cb2338dd6a6fdcfe52 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
ffdb6e87c8
commit
f27cb243c2
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@ -17,14 +17,13 @@
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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#include "cbfs.h"
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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@ -34,42 +33,14 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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}
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_reset->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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/* XHCI configuration */
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FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* sata configuration */
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -18,7 +18,6 @@ if BOARD_HP_ABM
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select AGESA_LEGACY
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select CPU_AMD_AGESA_FAMILY16_KB
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select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
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select SOUTHBRIDGE_AMD_AGESA_YANGTZE
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@ -21,7 +21,7 @@
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#include <PlatformMemoryConfiguration.h>
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#include "Filecode.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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@ -99,6 +99,13 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.DdiLinkList = DdiList
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchReset->Xhci1Enable = FALSE;
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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@ -116,7 +123,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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AGESA_STATUS Status;
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PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
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@ -138,14 +145,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
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InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------
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@ -159,7 +158,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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#define SEED_A 0x12
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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@ -178,7 +177,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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.InitMid = OemInitMid,
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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@ -20,7 +20,7 @@
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <southbridge/amd/agesa/hudson/pci_devs.h>
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#include <northbridge/amd/agesa/family16kb/pci_devs.h>
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@ -113,9 +113,6 @@ static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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@ -14,46 +14,35 @@
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/stages.h>
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#include <device/pnp_def.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/lapic.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cbmem.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct5104d/nct5104d.h>
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#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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u32 val, t32;
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u32 *addr32;
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u32 t32;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/* Set LPC decode enables. */
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/* For serial port option, plug-in card on LPC. */
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pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev, 0x44, 0xff03ffd5);
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hudson_lpc_port80();
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/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
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* even though the register is not documented in the Kabini BKDG.
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* Otherwise the serial output is bad code.
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*/
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outb(0xD2, 0xcd6);
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outb(0x00, 0xcd7);
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/* Enable the AcpiMmio space */
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outb(0x24, 0xcd6);
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outb(0x01, 0xcd7);
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@ -72,58 +61,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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t32 &= 0xffffff7b; // clear 2, 7
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*addr32 = t32;
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if (!cpu_init_detectedx && boot_cpu()) {
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post_code(0x30);
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post_code(0x31);
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nct5104d_enable_uartd(SERIAL_DEV);
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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report_bist_failure(bist);
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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post_code(0x37);
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agesawrapper_amdinitreset();
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post_code(0x38);
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printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
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post_code(0x39);
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agesawrapper_amdinitearly();
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int s3resume = acpi_is_wakeup_s3();
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if (!s3resume) {
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post_code(0x40);
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agesawrapper_amdinitpost();
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post_code(0x41);
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agesawrapper_amdinitenv();
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/* TODO: Disable cache is not ok. */
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disable_cache_as_ram();
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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agesawrapper_amdinitresume();
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amd_initcpuio();
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agesawrapper_amds3laterestore();
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post_code(0x61);
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prepare_for_resume();
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}
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nct5104d_enable_uartd(SERIAL_DEV);
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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#if 0
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/* Was before copy_and_run. */
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outb(0xEA, 0xCD6);
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outb(0x1, 0xcd7);
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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#endif
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