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mb/amd/gardenia,padmelon/devicetree: explicitly enable IOMMU device 

PCI devices that aren't present in the devicetree will be treated as
enabled. Since the chipset devicetree that will be added in a follow-up
patch disables this device by default, explicitly enable the IOMMU
device on the Stoneyridge mainboards that don't disable it to keep the
same behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a2cdd00abe8309244829dc633dd8a9ca0038dfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68313
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-10-12 23:14:44 +02:00
parent 30b3660956
commit f2812dfe53
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/amd/gardenia/devicetree.cb
View File

@ -13,6 +13,7 @@ chip soc/amd/stoneyridge
device domain 0 on
subsystemid 0x1022 0x1410 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge

1
src/mainboard/amd/padmelon/devicetree.cb
View File

@ -10,6 +10,7 @@ chip soc/amd/stoneyridge
device domain 0 on
subsystemid 0x1022 0x1410 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x9874
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge