intel/skylake: PL2 override changes

Override the default PL2 values with ones recommended by Intel.

BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
CQ-DEPEND=CL:321392

Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a
Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322454
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/chell/devicetree.cb

@@ -167,6 +167,9 @@ chip soc/intel/skylake
 	# I2C4 is 1.8V
 	register "SerialIoI2cVoltage[4]" = "1"
 
+	# PL2 override 15W
+	register "tdp_pl2_override" = "15"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end

src/mainboard/google/glados/devicetree.cb

@@ -167,6 +167,9 @@ chip soc/intel/skylake
 	# I2C4 is 1.8V
 	register "SerialIoI2cVoltage[4]" = "1"
 
+	# PL2 override 15W
+	register "tdp_pl2_override" = "15"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end

src/mainboard/google/lars/devicetree.cb

@@ -161,6 +161,9 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# PL2 override 25W
+	register "tdp_pl2_override" = "25"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -166,6 +166,9 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
+	# PL2 override 25W
+	register "tdp_pl2_override" = "25"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end