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mb/google/jecht: Prepare devicetree for PCH split 

Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 20:40:20 +02:00
parent c1f58e68fb
commit f2a295a5b6
1 changed files with 94 additions and 91 deletions
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19
src/mainboard/google/jecht/devicetree.cb
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@ -9,6 +9,16 @@ chip soc/intel/broadwell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
# chip soc/intel/broadwell/pch
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
@ -30,14 +40,6 @@ chip soc/intel/broadwell
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 off end # Serial I/O DMA
@ -111,5 +113,6 @@ chip soc/intel/broadwell
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal
# end
end
end