From f2af702df93a057fed54192abc8a907613841284 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 16 Nov 2018 12:08:41 +0100 Subject: [PATCH] soc/intel/braswell: Disable OS use of HPET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The timer interrupts don't appear when HPET is enabled. This result in Linux reporting 'MP-BIOS bug: 8254 timer not connected to IO-APIC' Enabling CONFIG_DISABLE_HPET disables OS use of HPET. Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation Hang or Slow Boot Issue. BUG=Intel #4800413 TEST=Portwell PQ7-M107 Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/29655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Michał Żygowski --- src/soc/intel/braswell/Kconfig | 7 +++++++ src/soc/intel/braswell/acpi.c | 7 +++++-- src/soc/intel/braswell/acpi/lpc.asl | 3 +++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 50c2802c6d..c383cdf892 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -128,4 +128,11 @@ config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/braswell/bootblock/timestamp.inc" +config DISABLE_HPET + bool "Disable the HPET device" + default n + help + Enable this to disable the HPET support + Solves the Linux MP-BIOS bug timer not connected. + endif diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 820e56a6f7..e7910724c4 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -486,8 +487,10 @@ unsigned long southcluster_write_acpi_tables(struct device *device, acpi_header_t *ssdt2; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); + if (!IS_ENABLED(CONFIG_DISABLE_HPET)) { + current = acpi_write_hpet(device, current, rsdp); + current = acpi_align_current(current); + } if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) { igd_opregion_t *opregion; diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 0a8b8bc081..ce83009a1b 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -47,6 +48,7 @@ Device (LPCB) }) } +#if !IS_ENABLED(CONFIG_DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) @@ -62,6 +64,7 @@ Device (LPCB) Memory32Fixed(ReadOnly, 0xfed00000, 0x400) }) } +#endif Device(PIC) /* 8259 Interrupt Controller */ {