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soc/amd/morgana/gpio: Update gpio definitions for morgana 

Update the GPIO definitions for morgana per PPR #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fa4aaf81b5487f7548f430cb35630aca8be732f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2022-10-13 13:15:22 -04:00 committed by Felix Held
parent 4ee037e8f0
commit f2b36036c7
2 changed files with 11 additions and 40 deletions
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2
src/soc/amd/morgana/gpio.c
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@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Update for Morgana */
#include <amdblocks/gpio.h>
#include <soc/gpio.h>
#include <types.h>

49
src/soc/amd/morgana/include/soc/gpio.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Update for Morgana */
#ifndef AMD_MORGANA_GPIO_H
#define AMD_MORGANA_GPIO_H
@ -33,8 +31,6 @@
#define GPIO_10 10
#define GPIO_11 11
#define GPIO_12 12
#define GPIO_13 13
#define GPIO_14 14
#define GPIO_16 16
#define GPIO_17 17
#define GPIO_18 18
@ -118,30 +114,20 @@
#define GPIO_3_IOMUX_GPIOxx 0
#define GPIO_4_IOMUX_GPIOxx 0
#define GPIO_5_IOMUX_GPIOxx 0
#define GPIO_5_IOMUX_DEVSLP0 1
#define GPIO_6_IOMUX_GPIOxx 0
#define GPIO_6_IOMUX_DEVSLP1 1
#define GPIO_6_IOMUX_MDIO0_SCL 2
#define GPIO_7_IOMUX_GPIOxx 0
#define GPIO_7_IOMUX_SVI_RST_L 1
#define GPIO_8_IOMUX_GPIOxx 0
#define GPIO_8_IOMUX_TMU_CLK_OUT0 1
#define GPIO_8_IOMUX_TMU_CLK_OUT1 2
#define GPIO_9_IOMUX_GPIOxx 0
/* GPIO 9 IOMUX == 1 is also GPIOxx */
#define GPIO_9_IOMUX_MDIO2_SCL 2
#define GPIO_10_IOMUX_GPIOxx 0
#define GPIO_10_IOMUX_S0A3_GPIO 1
/* GPIO 10 IOMUX == 2 is also GPIOxx */
#define GPIO_10_IOMUX_DF_VRCONTEXT_0 3
#define GPIO_11_IOMUX_GPIOxx 0
#define GPIO_11_IOMUX_BLINK 1
#define GPIO_11_IOMUX_MDIO3_SDA 2
#define GPIO_12_IOMUX_LLB_L 0
#define GPIO_12_IOMUX_GPIOxx 1
#define GPIO_12_IOMUX_LPC_PME_L 2
#define GPIO_13_IOMUX_USB_SBTX_0 0
#define GPIO_13_IOMUX_GPIOxx 1
#define GPIO_14_IOMUX_USB_SBTX_1 0
#define GPIO_14_IOMUX_GPIOxx 1
#define GPIO_16_IOMUX_USB_OC0_L 0
#define GPIO_16_IOMUX_GPIOxx 1
#define GPIO_17_IOMUX_USB_OC1_L 0
@ -159,13 +145,12 @@
#define GPIO_21_IOMUX_ESPI_RESET_L 0
#define GPIO_21_IOMUX_KBRST_L 1
#define GPIO_21_IOMUX_GPIOxx 2
#define GPIO_22_IOMUX_LDRQ0_L 0
#define GPIO_22_IOMUX_ESPI_ALERT_D1 1
#define GPIO_22_IOMUX_GPIOxx 2
#define GPIO_22_IOMUX_ESPI_ALERT_D1 0
#define GPIO_22_IOMUX_GPIOxx 1
/* GPIO 22 IOMUX == 2 is also GPIOxx */
#define GPIO_22_IOMUX_SD0_CMD 3
#define GPIO_23_IOMUX_AC_PRES 0
#define GPIO_23_IOMUX_GPIOxx 1
#define GPIO_23_IOMUX_MDIO2_SDA 2
#define GPIO_24_IOMUX_USB_OC3_L 0
#define GPIO_24_IOMUX_GPIOxx 1
#define GPIO_26_IOMUX_PCIE_RST0_L 0
@ -181,22 +166,18 @@
#define GPIO_31_IOMUX_GPIOxx 1
#define GPIO_32_IOMUX_GPIOxx 0
#define GPIO_32_IOMUX_LPC_RST_L 1
#define GPIO_32_IOMUX_MDIO3_SCL 2
#define GPIO_38_IOMUX_CLK_REQ5_L 0
#define GPIO_38_IOMUX_GPIOxx 1
#define GPIO_38_IOMUX_MDIO1_SDA 2
#define GPIO_39_IOMUX_CLK_REQ6_L 0
#define GPIO_39_IOMUX_GPIOxx 1
#define GPIO_39_IOMUX_MDIO1_SCL 2
#define GPIO_40_IOMUX_GPIOxx 0
/* GPIO 40 IOMUX == 1 is also GPIOxx */
#define GPIO_40_IOMUX_MDIO0_SDA 2
#define GPIO_42_IOMUX_GPIOxx 0
#define GPIO_42_IOMUX_DF_VRCONTEXT_1 1
#define GPIO_67_IOMUX_SPI_ROM_REQ 0
#define GPIO_67_IOMUX_GPIOxx 1
#define GPIO_68_IOMUX_SPI1_DAT2 0
#define GPIO_68_IOMUX_GPIOxx 1
#define GPIO_68_IOMUX_SERIRQ 2
/* GPIO 68 IOMUX == 2 is also GPIOxx */
#define GPIO_68_IOMUX_SD0_DATA3 3
#define GPIO_69_IOMUX_SPI1_DAT3 0
#define GPIO_69_IOMUX_GPIOxx 1
@ -207,8 +188,7 @@
#define GPIO_74_IOMUX_GPIOxx 1
#define GPIO_74_IOMUX_GFX10_CAC_IPIO0 2
#define GPIO_75_IOMUX_SPI2_CS1_L 0
#define GPIO_75_IOMUX_LPCCLK1 1
#define GPIO_75_IOMUX_GPIOxx 2
#define GPIO_75_IOMUX_GPIOxx 1
#define GPIO_76_IOMUX_SPI_ROM_GNT 0
#define GPIO_76_IOMUX_GPIOxx 1
#define GPIO_77_IOMUX_SPI1_CLK 0
@ -221,7 +201,6 @@
#define GPIO_78_IOMUX_SD0_DATA1 3
#define GPIO_79_IOMUX_SPI1_CS3_L 0
#define GPIO_79_IOMUX_GPIOxx 1
#define GPIO_79_IOMUX_LPC_CLKRUN_L 2
#define GPIO_80_IOMUX_SPI1_DAT1 0
#define GPIO_80_IOMUX_GPIOxx 1
/* GPIO 80 IOMUX == 2 is also GPIOxx */
@ -233,7 +212,6 @@
#define GPIO_85_IOMUX_FANOUT0 0
#define GPIO_85_IOMUX_GPIOxx 1
#define GPIO_86_IOMUX_GPIOxx 0
#define GPIO_86_IOMUX_LPC_SMI_L 1
#define GPIO_89_IOMUX_GENINT1_L 0
#define GPIO_89_IOMUX_PSP_INTR0 1
#define GPIO_89_IOMUX_GPIOxx 2
@ -243,9 +221,7 @@
#define GPIO_91_IOMUX_SPKR 0
#define GPIO_91_IOMUX_GPIOxx 1
#define GPIO_92_IOMUX_CLK_REQ0_L 0
#define GPIO_92_IOMUX_SATA_IS0_L 1
#define GPIO_92_IOMUX_SATA_ZP0_L 2
#define GPIO_92_IOMUX_GPIOxx 3
#define GPIO_92_IOMUX_GPIOxx 1
#define GPIO_104_IOMUX_SPI2_DAT0 0
#define GPIO_104_IOMUX_GPIOxx 1
#define GPIO_105_IOMUX_SPI2_DAT1 0
@ -266,12 +242,9 @@
#define GPIO_115_IOMUX_GPIOxx 1
#define GPIO_116_IOMUX_CLK_REQ2_L 0
#define GPIO_116_IOMUX_GPIOxx 1
#define GPIO_130_IOMUX_SATA_ACT_L 0
#define GPIO_130_IOMUX_GPIOxx 1
#define GPIO_130_IOMUX_GPIOxx 0
#define GPIO_131_IOMUX_CLK_REQ3_L 0
#define GPIO_131_IOMUX_SATA_IS1_L 1
#define GPIO_131_IOMUX_SATA_ZP1_L 2
#define GPIO_131_IOMUX_GPIOxx 3
#define GPIO_131_IOMUX_GPIOxx 1
#define GPIO_132_IOMUX_CLK_REQ4_L 0
#define GPIO_132_IOMUX_OSCIN 1
#define GPIO_132_IOMUX_GPIOxx 2