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cpu/intel/car: Add EC software sync to Intel romstage 

Perform EC software sync in romstage, before memory training is started.
Because the ChromeOS EC will not currently perform USB-PD negotiation
until it jumps to running its RW code, this allows the system to get
access to more power earlier in the boot flow.

This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC.

BUG=b:112198832
BRANCH=none
TEST=EC software sync works in update and non-update case.
No significant effect on boot time (~6 ms).

Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2019-10-25 15:13:04 -06:00 committed by Patrick Georgi
parent baeced336a
commit f2cae5085c
1 changed files with 4 additions and 0 deletions
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4
src/cpu/intel/car/romstage.c
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@ -21,6 +21,7 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <program_loading.h> #include <program_loading.h>
#include <timestamp.h> #include <timestamp.h>
#include <security/vboot/vboot_common.h>
/* If we do not have a constrained _car_stack region size, use the /* If we do not have a constrained _car_stack region size, use the
following as a guideline for acceptable stack usage. */ following as a guideline for acceptable stack usage. */
@ -51,6 +52,9 @@ static void romstage_main(unsigned long bist)
for (i = 0; i < num_guards; i++) for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard; stack_base[i] = stack_guard;
if (CONFIG(VBOOT_EARLY_EC_SYNC))
vboot_sync_ec();
mainboard_romstage_entry(); mainboard_romstage_entry();
/* Check the stack. */ /* Check the stack. */