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Move and rename ARCH_STAGE_HAS_xxx_SECTION rules 

Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.

For consistency prefixes are changed from ARCH_ to ENV_.

Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-08-21 07:15:38 +03:00
parent 2f944f4da4
commit f2cc52b694
4 changed files with 20 additions and 36 deletions
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7
src/arch/x86/include/arch/memlayout.h
View File

@ -16,13 +16,6 @@
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
/* No .data or .bss sections. Cache as RAM is handled separately. */
#define ARCH_STAGE_HAS_DATA_SECTION 0
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif
#if (CONFIG_RAMTOP == 0)
# error "CONFIG_RAMTOP not configured"
#endif

18
src/include/memlayout.h
View File

@ -30,24 +30,6 @@
#define ARCH_CACHELINE_ALIGN_SIZE 64
#endif
/* Default to data as well as bss. */
#ifndef ARCH_STAGE_HAS_DATA_SECTION
#define ARCH_STAGE_HAS_DATA_SECTION 1
#endif
#ifndef ARCH_STAGE_HAS_BSS_SECTION
#define ARCH_STAGE_HAS_BSS_SECTION 1
#endif
/*
* Default is that currently ENV_PAYLOAD_LOADER enable stage, smm,
* and rmodules have a heap.
*/
#ifndef ARCH_STAGE_HAS_HEAP_SECTION
#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \
ENV_RMODULE)
#endif
#define STR(x) #x
#define ALIGN_COUNTER(align) \

25
src/include/rules.h
View File

@ -266,6 +266,23 @@
#define ENV_PAYLOAD_LOADER ENV_RAMSTAGE
#endif
#if CONFIG(ARCH_X86)
/* Indicates memory layout is determined by arch/x86/car.ld. */
#define ENV_CACHE_AS_RAM (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE)
/* No .data sections with execute-in-place from ROM. */
#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM
/* No .bss sections with execute-in-place from ROM. */
#define ENV_STAGE_HAS_BSS_SECTION !ENV_CACHE_AS_RAM
#else
/* Both .data and .bss, sometimes SRAM not DRAM. */
#define ENV_STAGE_HAS_DATA_SECTION 1
#define ENV_STAGE_HAS_BSS_SECTION 1
#define ENV_CACHE_AS_RAM 0
#endif
/* Currently rmodules, ramstage and smm have heap. */
#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM)
/**
* For pre-DRAM stages and post-CAR always build with simple device model, ie.
* PCI, PNP and CPU functions operate without use of devicetree. The reason
@ -281,12 +298,4 @@
#define __SIMPLE_DEVICE__
#endif
/* x86 specific. Indicates that the current stage is running with cache-as-ram
* enabled from the beginning of the stage in C code. */
#if defined(__PRE_RAM__)
#define ENV_CACHE_AS_RAM CONFIG(ARCH_X86)
#else
#define ENV_CACHE_AS_RAM 0
#endif
#endif /* _RULES_H */

6
src/lib/program.ld
View File

@ -85,7 +85,7 @@
#endif
/* Include data, bss, and heap in that order. Not defined for all stages. */
#if ARCH_STAGE_HAS_DATA_SECTION
#if ENV_STAGE_HAS_DATA_SECTION
.data . : {
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
_data = .;
@ -125,7 +125,7 @@
}
#endif
#if ARCH_STAGE_HAS_BSS_SECTION
#if ENV_STAGE_HAS_BSS_SECTION
.bss . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
@ -138,7 +138,7 @@
}
#endif
#if ARCH_STAGE_HAS_HEAP_SECTION
#if ENV_STAGE_HAS_HEAP_SECTION
.heap . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_heap = .;