sandybridge boards: Drop default `pci_mmio_size`

2 GiB is the default already.

Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/apple/macbookair4_2/devicetree.cb

@@ -23,8 +23,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0x0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"

src/mainboard/asus/maximus_iv_gene-z/devicetree.cb

@@ -11,8 +11,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x1043 0x844d inherit
 

src/mainboard/asus/p8h61-m_lx/devicetree.cb

@@ -11,8 +11,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x1043 0x844d inherit
 

src/mainboard/asus/p8h61-m_pro/devicetree.cb

@@ -10,7 +10,6 @@ chip northbridge/intel/sandybridge
 			device lapic 0xacac off end
 		end
 	end
-	register "pci_mmio_size" = "2048"
 	device domain 0x0 on
 		device pci 00.0 on end	# Host bridge
 		device pci 01.0 on end	# PCIe bridge for discrete graphics (PCIEX16_1)

src/mainboard/asus/p8z77-v_lx2/devicetree.cb

@@ -10,7 +10,6 @@ chip northbridge/intel/sandybridge
 			device lapic 0xacac off end
 		end
 	end
-	register "pci_mmio_size" = "2048"
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
 		device pci 00.0 on  end		# Host bridge

src/mainboard/biostar/th61-itx/devicetree.cb

@@ -10,7 +10,6 @@ chip northbridge/intel/sandybridge
 			device lapic 0xacac off	end
 		end
 	end
-	register "pci_mmio_size" = "2048"
 	device domain 0 on
 		subsystemid 0x1565 0x3108 inherit
 

src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb

@@ -11,8 +11,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x1458 0x5000 inherit
 		device pci 00.0 on	# Host bridge

src/mainboard/gigabyte/ga-h61m-series/devicetree.cb

@@ -10,7 +10,6 @@ chip northbridge/intel/sandybridge
 			device lapic 0xacac off	end
 		end
 	end
-	register "pci_mmio_size" = "2048"
 	device domain 0 on
 		subsystemid 0x1458 0x5000 inherit
 

src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb

@@ -16,8 +16,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0x0 on
 		subsystemid 0x103c 0x1495 inherit
 

src/mainboard/hp/z220_sff_workstation/devicetree.cb

@@ -16,8 +16,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0x0 on
 		subsystemid 0x103c 0x1791 inherit
 

src/mainboard/lenovo/t420/devicetree.cb

@@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21ce inherit
 

src/mainboard/lenovo/t420s/devicetree.cb

@@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21d2 inherit
 

src/mainboard/lenovo/t430s/devicetree.cb

@@ -26,8 +26,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21fb inherit
 

src/mainboard/lenovo/t520/devicetree.cb

@@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21cf inherit
 

src/mainboard/lenovo/t530/devicetree.cb

@@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21f6 inherit
 

src/mainboard/lenovo/x220/devicetree.cb

@@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
-	register "pci_mmio_size" = "2048"
-
 	device domain 0 on
 		subsystemid 0x17aa 0x21db inherit