From f2e8865d76107dff6113a637a232fc4cf0720be8 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 7 Apr 2023 20:10:05 -0500 Subject: [PATCH] soc/amd/common/blk/pcie: Program LTR max latencies PCIe bridges need to provide the LTR (latency tolerance reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.049ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288 Reviewed-by: Marshall Dawson Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/block/pci/pcie_gpp.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 0ce3268501..0f983d04be 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -47,6 +47,20 @@ static void acpi_device_write_gpp_pci_dev(const struct device *dev) acpigen_pop_len(); /* Scope */ } +/* Latency tolerance reporting, max snoop/non-snoop latency value 1.049ms */ +#define PCIE_LTR_MAX_LATENCY_1049US 0x1001 + +static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop) +{ + *max_snoop = PCIE_LTR_MAX_LATENCY_1049US; + *max_nosnoop = PCIE_LTR_MAX_LATENCY_1049US; +} + +static struct pci_operations pcie_ops = { + .get_ltr_max_latencies = pcie_get_ltr_max_latencies, + .set_subsystem = pci_dev_set_subsystem, +}; + struct device_operations amd_internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -65,4 +79,5 @@ struct device_operations amd_external_pcie_gpp_ops = { .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, + .ops_pci = &pcie_ops, };