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Remove some DOS line endings accidentially introduced in r3014. 

No code lines affected, so svn blame will not be messed up.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2008-01-08 17:28:35 +00:00
parent 4d1aa0a9eb
commit f2ecb74023
1 changed files with 11 additions and 11 deletions
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22
src/cpu/amd/car/cache_as_ram.inc
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@ -1,6 +1,6 @@
/* /*
* This file is part of the LinuxBIOS project. * This file is part of the LinuxBIOS project.
* *
* Copyright (C) 2005-2007 Advanced Micro Devices, Inc. * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
@ -15,11 +15,11 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize DCACHE_RAM_SIZE #define CacheSize DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize) #define CacheBase (0xd0000 - CacheSize)
/* leave some space for global variable to pass to RAM stage */ /* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE #define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
@ -36,7 +36,7 @@
/*for normal part %ebx already contain cpu_init_detected from fallback call */ /*for normal part %ebx already contain cpu_init_detected from fallback call */
cache_as_ram_setup: cache_as_ram_setup:
movb $0xA0, %al movb $0xA0, %al
outb %al, $0x80 outb %al, $0x80
@ -107,7 +107,7 @@ enable_fixed_mtrr_dram_modify:
/* Clear all MTRRs */ /* Clear all MTRRs */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
testl %eax, %eax testl %eax, %eax
@ -245,7 +245,7 @@ clear_fixed_var_mtrr_out:
movb $0xA1, %al movb $0xA1, %al
outb %al, $0x80 outb %al, $0x80
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
@ -259,7 +259,7 @@ clear_fixed_var_mtrr_out:
bt $8, %eax /*BSC */ bt $8, %eax /*BSC */
jnc CAR_FAM10_ap jnc CAR_FAM10_ap
#endif #endif
movb $0xA2, %al movb $0xA2, %al
outb %al, $0x80 outb %al, $0x80
@ -280,7 +280,7 @@ clear_fixed_var_mtrr_out:
/* set up the stack pointer */ /* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp movl %eax, %esp
movb $0xA3, %al movb $0xA3, %al
outb %al, $0x80 outb %al, $0x80
@ -316,7 +316,7 @@ CAR_FAM10_ap:
jc roll_cfg jc roll_cfg
rolb %cl, %bl rolb %cl, %bl
roll_cfg: roll_cfg:
/* calculate stack pointer */ /* calculate stack pointer */
movl $CacheSizeAPStack, %eax movl $CacheSizeAPStack, %eax
mull %ebx mull %ebx
@ -337,7 +337,7 @@ CAR_FAM10_ap_out:
/* Restore the BIST result */ /* Restore the BIST result */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set ebp ? No need */
movl %esp, %ebp movl %esp, %ebp
pushl %ebx /* init detected */ pushl %ebx /* init detected */