mb/google/deltaur: Remove GbE FMAP region

Deltan will be using the integrated Intel GbE for LAN
functionality. Deltaur will not have a LAN port, and so does not need
the GbE region. This patch adds a new FMAP descriptor file which
explicitly supports the GbE region (chromeos-gbe.fmd), and removes the
GbE region from chromeos.fmd.  Deltan is then assigned chromeos-gbe.fmd,
and Deltaur is assigned chromeos.fmd.

BUG=b:150165131
TEST=emerge-deltaur coreboot chromeos-bootimage
and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Wawrzynczak 2020-04-17 19:07:26 -06:00 committed by Patrick Georgi
parent ca584085d7
commit f3003657a0
3 changed files with 55 additions and 2 deletions

View File

@ -43,6 +43,11 @@ config DRIVER_TPM_I2C_ADDR
hex hex
default 0x50 default 0x50
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-gbe.fmd" if BOARD_GOOGLE_DELTAN
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_GOOGLE_DELTAUR
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE
string string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"

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@ -0,0 +1,49 @@
FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x606000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000
SI_GBE(PRESERVE)@0x101000 0x2000
SI_ME@0x103000 0x4ff000
SI_PDR(PRESERVE)@0x602000 0x4000
}
SI_BIOS@0x606000 0x19fa000 {
RW_DIAG@0x0 0x10ca000 {
RW_LEGACY(CBFS)@0x0 0x10ba000
DIAG_NVRAM@0x10ba000 0x10000
}
RW_SECTION_A@0x10ca000 0x280000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0
RW_FWID_A@0x27ffc0 0x40
}
RW_SECTION_B@0x134a000 0x280000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x26ffc0
RW_FWID_B@0x27ffc0 0x40
}
RW_MISC@0x15ca000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG(PRESERVE)@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
WP_RO@0x15fa000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x3000
COREBOOT(CBFS)@0x4000 0x3ec000
}
}
}
}

View File

@ -2,8 +2,7 @@ FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x606000 { SI_ALL@0x0 0x606000 {
SI_DESC@0x0 0x1000 SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000 SI_EC@0x1000 0x100000
SI_GBE(PRESERVE)@0x101000 0x2000 SI_ME@0x101000 0x501000
SI_ME@0x103000 0x4ff000
SI_PDR(PRESERVE)@0x602000 0x4000 SI_PDR(PRESERVE)@0x602000 0x4000
} }
SI_BIOS@0x606000 0x19fa000 { SI_BIOS@0x606000 0x19fa000 {