mb/google/deltaur: Remove GbE FMAP region
Deltan will be using the integrated Intel GbE for LAN functionality. Deltaur will not have a LAN port, and so does not need the GbE region. This patch adds a new FMAP descriptor file which explicitly supports the GbE region (chromeos-gbe.fmd), and removes the GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd, and Deltaur is assigned chromeos.fmd. BUG=b:150165131 TEST=emerge-deltaur coreboot chromeos-bootimage and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -43,6 +43,11 @@ config DRIVER_TPM_I2C_ADDR
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hex
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hex
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default 0x50
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default 0x50
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-gbe.fmd" if BOARD_GOOGLE_DELTAN
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_GOOGLE_DELTAUR
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config OVERRIDE_DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -0,0 +1,49 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x606000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE(PRESERVE)@0x101000 0x2000
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SI_ME@0x103000 0x4ff000
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SI_PDR(PRESERVE)@0x602000 0x4000
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}
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SI_BIOS@0x606000 0x19fa000 {
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RW_DIAG@0x0 0x10ca000 {
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RW_LEGACY(CBFS)@0x0 0x10ba000
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DIAG_NVRAM@0x10ba000 0x10000
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}
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RW_SECTION_A@0x10ca000 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x134a000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0x15ca000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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WP_RO@0x15fa000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0x3000
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COREBOOT(CBFS)@0x4000 0x3ec000
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}
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}
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}
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}
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@ -2,8 +2,7 @@ FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x606000 {
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SI_ALL@0x0 0x606000 {
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SI_DESC@0x0 0x1000
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_EC@0x1000 0x100000
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SI_GBE(PRESERVE)@0x101000 0x2000
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SI_ME@0x101000 0x501000
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SI_ME@0x103000 0x4ff000
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SI_PDR(PRESERVE)@0x602000 0x4000
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SI_PDR(PRESERVE)@0x602000 0x4000
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}
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}
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SI_BIOS@0x606000 0x19fa000 {
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SI_BIOS@0x606000 0x19fa000 {
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