nb/intel/haswell: Use the common MRC cache driver
This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -16,7 +16,7 @@
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config NORTHBRIDGE_INTEL_HASWELL
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config NORTHBRIDGE_INTEL_HASWELL
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bool
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bool
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select CPU_INTEL_HASWELL
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select CPU_INTEL_HASWELL
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select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select INTEL_GMA_ACPI
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select RELOCATABLE_RAMSTAGE
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select RELOCATABLE_RAMSTAGE
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@ -39,11 +39,6 @@ config CACHE_MRC_SIZE_KB
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int
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int
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default 512
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default 512
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config MRC_CACHE_SIZE
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hex
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depends on !CHROMEOS
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default 0x10000
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config DCACHE_RAM_BASE
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config DCACHE_RAM_BASE
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hex
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hex
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default 0xff7c0000
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default 0xff7c0000
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@ -36,16 +36,4 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
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mrc.bin-position := 0xfffa0000
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mrc.bin-position := 0xfffa0000
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mrc.bin-type := mrc
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mrc.bin-type := mrc
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ifneq ($(CONFIG_CHROMEOS),y)
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$(obj)/mrc.cache: $(obj)/config.h
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dd if=/dev/zero count=1 \
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bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
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tr '\000' '\377' > $@
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cbfs-files-y += mrc.cache
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mrc.cache-file := $(obj)/mrc.cache
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mrc.cache-align := 0x10000
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mrc.cache-type := mrc_cache
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endif
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endif
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endif
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@ -22,42 +22,44 @@
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#include <halt.h>
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#include <halt.h>
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#include <ip_checksum.h>
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#include <ip_checksum.h>
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#include <memory_info.h>
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#include <memory_info.h>
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#include <northbridge/intel/common/mrc_cache.h>
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#include <mrc_cache.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/mc146818rtc.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <device/dram/ddr3.h>
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#include <device/dram/ddr3.h>
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#include <smbios.h>
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#include <smbios.h>
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#include <spd.h>
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#include <spd.h>
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#include <security/vboot/vboot_common.h>
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#include <security/vboot/vboot_common.h>
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#include <commonlib/region.h>
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#include "raminit.h"
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#include "raminit.h"
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#include "pei_data.h"
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#include "pei_data.h"
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#include "haswell.h"
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#include "haswell.h"
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#define MRC_CACHE_VERSION 1
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void save_mrc_data(struct pei_data *pei_data)
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void save_mrc_data(struct pei_data *pei_data)
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{
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{
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/* Save the MRC S3 restore data to cbmem */
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/* Save the MRC S3 restore data to cbmem */
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store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len);
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
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pei_data->mrc_output, pei_data->mrc_output_len);
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}
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}
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static void prepare_mrc_cache(struct pei_data *pei_data)
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static void prepare_mrc_cache(struct pei_data *pei_data)
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{
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{
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struct mrc_data_container *mrc_cache;
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struct region_device rdev;
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// preset just in case there is an error
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// preset just in case there is an error
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pei_data->mrc_input = NULL;
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pei_data->mrc_input = NULL;
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pei_data->mrc_input_len = 0;
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pei_data->mrc_input_len = 0;
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if ((mrc_cache = find_current_mrc_cache()) == NULL) {
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if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev))
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/* error message printed in find_current_mrc_cache */
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/* error message printed in find_current_mrc_cache */
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return;
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return;
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}
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pei_data->mrc_input = mrc_cache->mrc_data;
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pei_data->mrc_input = rdev_mmap_full(&rdev);
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pei_data->mrc_input_len = mrc_cache->mrc_data_size;
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pei_data->mrc_input_len = region_device_sz(&rdev);
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printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n",
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printk(BIOS_DEBUG, "%s: at %p, size %x\n",
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__func__, pei_data->mrc_input,
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__func__, pei_data->mrc_input, pei_data->mrc_input_len);
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pei_data->mrc_input_len, mrc_cache->mrc_checksum);
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}
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}
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static const char* ecc_decoder[] = {
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static const char* ecc_decoder[] = {
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