fsp/fsp2_0/coffeelake: Update CFL FSP headers
Coffeelake FSP headers had been updated to version 7.0.3D.60. Original file location from https://github.com/IntelFsp/FSP/tree/master/ CoffeeLakeFspBinPkg/Include . BUG=N/A TEST=Build and flash, able to boot up into OS on whiskeylake rvp platform. Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28286 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
Martin Roth
parent
990d825196
commit
f3122426b8
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@ -37,19 +37,19 @@ are permitted provided that the following conditions are met:
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#pragma pack(1)
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#include <MemInfoHob.h>
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///
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/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
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///
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typedef struct {
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UINT8 Revision; ///< Chipset Init Info Revision
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UINT8 Rsvd[3]; ///< Reserved
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UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
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UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
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} CHIPSET_INIT_INFO;
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#include <MemInfoHob.h>
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///
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/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
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///
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typedef struct {
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UINT8 Revision; ///< Chipset Init Info Revision
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UINT8 Rsvd[3]; ///< Reserved
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UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
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UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
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} CHIPSET_INIT_INFO;
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/** Fsp M Configuration
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**/
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@ -331,9 +331,16 @@ typedef struct {
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**/
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UINT8 ScramblerSupport;
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/** Offset 0x00C8
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/** Offset 0x00C8 - Skip Multi-Processor Initialization
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When this is skipped, boot loader must initialize processors before SilicionInit
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API. </b>0: Initialize; <b>1: Skip
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace1[16];
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UINT8 SkipMpInit;
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/** Offset 0x00C9
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**/
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UINT8 UnusedUpdSpace1[15];
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/** Offset 0x00D8 - SPD Profile Selected
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Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
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@ -479,7 +486,9 @@ typedef struct {
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UINT8 CpuTraceHubMemReg1Size;
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/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
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Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
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Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message
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to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,
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and <b>1: Enable</b> for all other CPU's
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$EN_DIS
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**/
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UINT8 PeciC10Reset;
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@ -949,7 +958,7 @@ typedef struct {
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/** Offset 0x0205 - Maximum Core Turbo Ratio Override
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Maximum core turbo ratio override allows to increase CPU core frequency beyond the
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fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
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fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
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**/
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UINT8 CoreMaxOcRatio;
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@ -959,13 +968,15 @@ typedef struct {
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**/
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UINT8 CoreVoltageMode;
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/** Offset 0x0207
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/** Offset 0x0207 - Program Cache Attributes
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Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace6;
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UINT8 DisableMtrrProgram;
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/** Offset 0x0208 - Maximum clr turbo ratio override
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Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
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fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
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fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
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**/
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UINT8 RingMaxOcRatio;
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@ -1116,7 +1127,7 @@ typedef struct {
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/** Offset 0x0227
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**/
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UINT8 UnusedUpdSpace7;
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UINT8 UnusedUpdSpace6;
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/** Offset 0x0228 - PrmrrSize
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0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
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@ -1861,12 +1872,12 @@ typedef struct {
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UINT8 RhActProbability;
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/** Offset 0x04C1 - RAPL PL 2 WindowX
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Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
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Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
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**/
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UINT8 RaplLim2WindX;
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/** Offset 0x04C2 - RAPL PL 2 WindowY
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Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
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Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
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**/
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UINT8 RaplLim2WindY;
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@ -1881,52 +1892,52 @@ typedef struct {
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UINT8 RaplLim1WindY;
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/** Offset 0x04C5 - RAPL PL 2 Power
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range[0;2^14-1]= [2047.875;0]in W, (224= Def)
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range[0;2^14-1]= [2047.875;0]in W, (222= Def)
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**/
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UINT16 RaplLim2Pwr;
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/** Offset 0x04C7 - RAPL PL 1 Power
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range[0;2^14-1]= [2047.875;0]in W, (224= Def)
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range[0;2^14-1]= [2047.875;0]in W, (0= Def)
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**/
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UINT16 RaplLim1Pwr;
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/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 WarmThresholdCh0Dimm0;
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/** Offset 0x04CA - Warm Threshold Ch0 Dimm1
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 WarmThresholdCh0Dimm1;
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/** Offset 0x04CB - Warm Threshold Ch1 Dimm0
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 WarmThresholdCh1Dimm0;
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/** Offset 0x04CC - Warm Threshold Ch1 Dimm1
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 WarmThresholdCh1Dimm1;
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/** Offset 0x04CD - Hot Threshold Ch0 Dimm0
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 HotThresholdCh0Dimm0;
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/** Offset 0x04CE - Hot Threshold Ch0 Dimm1
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 HotThresholdCh0Dimm1;
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/** Offset 0x04CF - Hot Threshold Ch1 Dimm0
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 HotThresholdCh1Dimm0;
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/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
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range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
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**/
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UINT8 HotThresholdCh1Dimm1;
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@ -2072,7 +2083,7 @@ typedef struct {
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/** Offset 0x04ED - Throttler CKEMin Timer
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Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
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Dfault is 0x30
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Default is 0x30
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**/
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UINT8 ThrtCkeMinTmr;
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@ -2286,9 +2297,34 @@ typedef struct {
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**/
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UINT8 DualDimmPerChannelBoardType;
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/** Offset 0x0510
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/** Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation
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Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population.
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Disable(Default)=0, Enable=1
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$EN_DIS
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**/
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UINT8 ReservedFspmUpd[15];
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UINT8 Ddr4MixedUDimm2DpcLimit;
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/** Offset 0x0511 - CFL Reserved
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Reserved FspmConfig CFL
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$EN_DIS
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**/
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UINT8 ReservedFspmUpdCfl[2];
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/** Offset 0x0513 - Memory Test on Warm Boot
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Run Base Memory Test on Warm Boot
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0:Disable, 1:Enable
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**/
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UINT8 MemTestOnWarmBoot;
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/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR
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Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T +
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BYTE_LENGTH (4). Default is 0x40
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**/
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UINT8 ThrtCkeMinTmrLpddr;
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/** Offset 0x0515
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**/
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UINT8 ReservedFspmUpd[10];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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@ -2513,7 +2549,7 @@ typedef struct {
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/** Offset 0x0579
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**/
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UINT8 UnusedUpdSpace9;
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UINT8 UnusedUpdSpace8;
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/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
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Range: 0-65535, default is 1000. @warning Do not change from the default
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@ -2596,14 +2632,13 @@ typedef struct {
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UINT8 SmbusSpdWriteDisable;
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/** Offset 0x059B - ChipsetInit HECI message
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Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
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If disabled, it prevents from sending ChipsetInit HECI message.
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DEPRECATED
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$EN_DIS
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**/
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UINT8 ChipsetInitMessage;
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/** Offset 0x059C - Bypass ChipsetInit sync reset.
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0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
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DEPRECATED
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$EN_DIS
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**/
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UINT8 BypassPhySyncReset;
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@ -2788,7 +2823,7 @@ typedef struct {
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/** Offset 0x051F
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**/
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UINT8 UnusedUpdSpace8;
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UINT8 UnusedUpdSpace7;
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/** Offset 0x0520
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**/
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