Route device IRQ through PCI bridge instead in mptable.
Don't enable pin0 for ioapic of io-4. 1. apic error in kernel for MB with mcp55+io55 2. some pcie-cards could have pci bridge there, so need to put entries for device under them in mptable. Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
Stefan Reinauer
parent
8eff1e3d04
commit
f327d9f954
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@ -248,6 +248,10 @@ void smp_write_intsrc(struct mp_config_table *mc,
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unsigned char irqtype, unsigned short irqflag,
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unsigned char srcbus, unsigned char srcbusirq,
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unsigned char dstapic, unsigned char dstirq);
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void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
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unsigned char irqtype, unsigned short irqflag,
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struct device *dev,
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unsigned char dstapic, unsigned char *dstirq);
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void smp_write_lintsrc(struct mp_config_table *mc,
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unsigned char irqtype, unsigned short irqflag,
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unsigned char srcbusid, unsigned char srcbusirq,
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@ -1,6 +1,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <arch/smp/mpspec.h>
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#include <string.h>
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@ -26,8 +27,7 @@ void *smp_write_floating_table(unsigned long addr)
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void *v;
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/* 16 byte align the table address */
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addr += 15;
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addr &= ~15;
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addr = (addr + 0xf) & (~0xf);
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v = (void *)addr;
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mf = v;
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@ -52,8 +52,8 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
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{
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struct intel_mp_floating *mf;
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void *v;
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v = (void *)addr;
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v = (void *)addr;
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mf = v;
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mf->mpf_signature[0] = '_';
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mf->mpf_signature[1] = 'M';
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@ -204,6 +204,58 @@ void smp_write_intsrc(struct mp_config_table *mc,
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#endif
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}
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void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
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unsigned char irqtype, unsigned short irqflag,
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struct device *dev,
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unsigned char dstapic, unsigned char *dstirq)
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{
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struct device *child;
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int linkn;
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int i;
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int srcbus;
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int slot;
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struct bus *link;
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unsigned char dstirq_x[4];
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for (linkn = 0; linkn < dev->links; linkn++) {
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link = &dev->link[linkn];
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child = link->children;
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srcbus = link->secondary;
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while (child) {
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if (child->path.type != DEVICE_PATH_PCI)
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goto next;
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slot = (child->path.u.pci.devfn >> 3);
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/* round pins */
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for (i = 0; i < 4; i++)
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dstirq_x[i] = dstirq[(i + slot) % 4];
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if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
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/* pci device */
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printk_debug("route irq: %s %04x\n", dev_path(child));
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for (i = 0; i < 4; i++)
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smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]);
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goto next;
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}
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switch (child->class>>8) {
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case PCI_CLASS_BRIDGE_PCI:
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case PCI_CLASS_BRIDGE_PCMCIA:
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case PCI_CLASS_BRIDGE_CARDBUS:
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printk_debug("route irq bridge: %s %04x\n", dev_path(child));
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smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x);
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}
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next:
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child = child->sibling;
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}
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}
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}
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void smp_write_lintsrc(struct mp_config_table *mc,
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unsigned char irqtype, unsigned short irqflag,
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@ -35,7 +35,7 @@
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// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
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struct mb_sysconf_t mb_sysconf;
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unsigned pci1234x[] =
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unsigned pci1234x[] =
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{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
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//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
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0x0000ff0,
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@ -47,7 +47,7 @@ unsigned pci1234x[] =
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// 0x0000ff0,
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// 0x0000ff0
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};
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unsigned hcdnx[] =
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unsigned hcdnx[] =
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{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
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0x20202020,
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0x20202020,
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@ -98,18 +98,19 @@ void get_bus_conf(void)
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device_t dev;
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int i, j;
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if(get_bus_conf_done==1) return; //do it only once
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if (get_bus_conf_done)
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return; //do it only once
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get_bus_conf_done = 1;
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sysconf.mb = &mb_sysconf;
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m = sysconf.mb;
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memset(m, 0, sizeof(struct mb_sysconf_t));
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sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
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for(i=0;i<sysconf.hc_possible_num; i++) {
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for (i = 0; i < sysconf.hc_possible_num; i++) {
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sysconf.pci1234[i] = pci1234x[i];
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sysconf.hcdn[i] = hcdnx[i];
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}
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@ -121,77 +122,41 @@ void get_bus_conf(void)
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m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
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m->bus_type[0] = 1; //pci
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m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
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/* MCP55 */
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dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
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if (dev) {
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m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
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}
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m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff;
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for(i=2; i<8;i++) {
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dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
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if (dev) {
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m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
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}
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}
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for (i = 0; i < sysconf.hc_possible_num; i++) {
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unsigned busn_min, busn_max;
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if(m->bus_mcp55[2]) {
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for(i=0;i<2; i++) {
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dev = dev_find_slot(m->bus_mcp55[2], PCI_DEVFN(0, i));
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if(dev) {
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m->bus_pcix[0] = m->bus_mcp55[2];
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m->bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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}
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for(i=0; i< sysconf.hc_possible_num; i++) {
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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if (!(sysconf.pci1234[i] & 0x1))
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continue;
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unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
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unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
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for (j = busn; j <= busn_max; j++)
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busn_min = (sysconf.pci1234[i] >> 16) & 0xff;
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busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
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for (j = busn_min; j <= busn_max; j++)
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m->bus_type[j] = 1;
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if(m->bus_isa <= busn_max)
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if(m->bus_isa <= busn_max)
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m->bus_isa = busn_max + 1;
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printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
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printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
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}
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/* MCP55b */
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for(i=1; i< sysconf.hc_possible_num; i++) {
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if (!(sysconf.pci1234[i] & 0x0f) ) continue;
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for (i = 1; i < sysconf.hc_possible_num; i++) {
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if (!(sysconf.pci1234[i] & 0x0f))
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continue;
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// check hcid type here
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sysconf.hcid[i] = get_hcid(i);
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if (!sysconf.hcid[i]) continue; //unknown co processor
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if (!sysconf.hcid[i])
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continue; //unknown co processor
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m->bus_mcp55b[0] = (sysconf.pci1234[1]>>16) & 0xff;
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m->bus_mcp55b[1] = m->bus_mcp55b[0]+1; //fake pci
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for(i=2; i<8;i++) {
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dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x0a + i - 2 , 0));
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if (dev) {
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m->bus_mcp55b[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55b[0], m->sbdnb + 0x0a + i - 2 );
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}
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}
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m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff;
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}
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/*I/O APICs: APIC ID Version State Address*/
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#if CONFIG_LOGICAL_CPUS==1
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apicid_base = get_apicid_base(2);
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#else
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apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
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#else
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apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
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#endif
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m->apicid_mcp55 = apicid_base+0;
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m->apicid_mcp55b = apicid_base+1;
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@ -78,15 +78,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq = (void *)(addr);
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v = (uint8_t *)(addr);
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->rtr_bus = m->bus_mcp55[0];
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pirq->rtr_bus = m->bus_mcp55;
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pirq->rtr_devfn = ((sbdn+6)<<3)|0;
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pirq->exclusive_irqs = 0;
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pirq->rtr_vendor = 0x10de;
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pirq->rtr_device = 0x0370;
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@ -97,10 +97,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq_info = (void *) ( &pirq->checksum + 1);
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slot_num = 0;
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//pci bridge
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write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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for(i=1; i< sysconf.hc_possible_num; i++) {
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for (i = 1; i < sysconf.hc_possible_num; i++) {
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if(!(sysconf.pci1234[i] & 0x1) ) continue;
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unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
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unsigned devn = sysconf.hcdn[i] & 0xff;
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@ -109,10 +109,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq_info++; slot_num++;
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}
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pirq->size = 32 + 16 * slot_num;
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pirq->size = 32 + 16 * slot_num;
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for (i = 0; i < pirq->size; i++)
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sum += v[i];
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sum += v[i];
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sum = pirq->checksum - sum;
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@ -24,12 +24,11 @@
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struct mb_sysconf_t {
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unsigned char bus_isa;
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unsigned char bus_mcp55[8]; //1
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unsigned char bus_mcp55b[8];//a
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unsigned char bus_mcp55;
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unsigned char bus_mcp55b;
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unsigned apicid_mcp55;
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unsigned apicid_mcp55b;
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unsigned bus_type[256];
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unsigned char bus_pcix[3]; // under bus_mcp55_2
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unsigned sbdnb;
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@ -39,6 +39,7 @@ void *smp_write_config_table(void *v)
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unsigned sbdn;
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int i,j;
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unsigned char apicpin[4];
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -65,8 +66,8 @@ void *smp_write_config_table(void *v)
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/*Bus: Bus ID Type*/
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/* define bus and isa numbers */
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for(j= 0; j < 256 ; j++) {
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if(m->bus_type[j])
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for (j = 0; j < 256 ; j++) {
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if (m->bus_type[j])
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smp_write_bus(mc, j, "PCI ");
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}
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smp_write_bus(mc, m->bus_isa, "ISA ");
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@ -77,38 +78,43 @@ void *smp_write_config_table(void *v)
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struct resource *res;
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uint32_t dword;
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dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
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dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
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}
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/* Initialize interrupt mapping*/
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dword = pci_read_config32(dev, 0x74);
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dword &= ~(1<<15);
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dword |= 1<<2;
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pci_write_config32(dev, 0x74, dword);
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dword = 0x43c6c643;
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pci_write_config32(dev, 0x7c, dword);
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pci_write_config32(dev, 0x7c, dword);
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dword = 0x81001a00;
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pci_write_config32(dev, 0x80, dword);
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dword = 0xd00012d2;
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dword = 0xd00012d2;
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pci_write_config32(dev, 0x84, dword);
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}
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if(m->bus_mcp55b[0]) {
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dev = dev_find_slot(m->bus_mcp55b[0], PCI_DEVFN(m->sbdnb + 0x1,0));
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if (m->bus_mcp55b) {
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dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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if (res)
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smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
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}
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dword = 0x43c60000;
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pci_write_config32(dev, 0x7c, dword);
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pci_write_config32(dev, 0x7c, dword);
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dword = 0x81000000;
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pci_write_config32(dev, 0x80, dword);
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dword = 0xd00002d0;
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dword = 0xd00002d0;
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pci_write_config32(dev, 0x84, dword);
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}
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@ -116,8 +122,8 @@ void *smp_write_config_table(void *v)
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}
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}
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
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@ -131,63 +137,65 @@ void *smp_write_config_table(void *v)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
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|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
|
||||
|
||||
for(j=7; j>=2; j--) {
|
||||
if(!m->bus_mcp55[j]) continue;
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
|
||||
}
|
||||
//Slot PCIE
|
||||
for (j = 2; j < 8; j++) {
|
||||
device_t dev;
|
||||
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
|
||||
if (!dev || !dev->enabled)
|
||||
continue;
|
||||
for (i = 0; i < 4; i++)
|
||||
apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
|
||||
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
|
||||
}
|
||||
|
||||
for(j=0; j<2; j++)
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x06+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
|
||||
}
|
||||
//Slot PCI 32
|
||||
{
|
||||
device_t dev;
|
||||
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
|
||||
if (dev && dev->enabled) {
|
||||
for (i = 0; i < 4; i++)
|
||||
apicpin[i] = 0x10 + (2+i)%4;
|
||||
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
|
||||
}
|
||||
}
|
||||
|
||||
if(m->bus_mcp55b[0]) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
|
||||
if (m->bus_mcp55b) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[0], ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
|
||||
|
||||
|
||||
for(j=7; j>=2; j--) {
|
||||
if(!m->bus_mcp55b[j]) continue;
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b[j], (0x00<<2)|i, m->apicid_mcp55b, 0x10 + (2+j+i+4-m->sbdnb%4)%4);
|
||||
//Slot PCIE
|
||||
for (j = 2; j < 8; j++) {
|
||||
device_t dev;
|
||||
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
|
||||
if (!dev || !dev->enabled)
|
||||
continue;
|
||||
for (i = 0; i < 4; i++) {
|
||||
apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4;
|
||||
}
|
||||
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin);
|
||||
}
|
||||
|
||||
}
|
||||
#if 1
|
||||
|
||||
if(m->bus_pcix[0]) {
|
||||
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[2], (4<<2)|i, m->apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
|
||||
}
|
||||
|
||||
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_pcix[1], (4<<2)|i, m->apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ static struct ioapicreg ioapicregvalues[] = {
|
|||
/* Be careful and don't write past the end... */
|
||||
};
|
||||
|
||||
static void setup_ioapic(unsigned long ioapic_base)
|
||||
static void setup_ioapic(unsigned long ioapic_base, int master)
|
||||
{
|
||||
int i;
|
||||
unsigned long value_low, value_high;
|
||||
|
|
@ -95,7 +95,14 @@ static void setup_ioapic(unsigned long ioapic_base)
|
|||
volatile unsigned long *l;
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
ioapicregvalues[0].value_high = lapicid()<<(56-32);
|
||||
if (master) {
|
||||
ioapicregvalues[0].value_high = lapicid()<<(56-32);
|
||||
ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
|
||||
}
|
||||
else {
|
||||
ioapicregvalues[0].value_high = NONE;
|
||||
ioapicregvalues[0].value_low = DISABLED;
|
||||
}
|
||||
|
||||
l = (unsigned long *) ioapic_base;
|
||||
|
||||
|
|
@ -121,14 +128,14 @@ static void setup_ioapic(unsigned long ioapic_base)
|
|||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define SLOW_CPU_OFF 0
|
||||
#define SLOW_CPU__ON 1
|
||||
#define SLOW_CPU_OFF 0
|
||||
#define SLOW_CPU__ON 1
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
static void lpc_common_init(device_t dev)
|
||||
static void lpc_common_init(device_t dev, int master)
|
||||
{
|
||||
uint8_t byte;
|
||||
uint32_t dword;
|
||||
|
|
@ -139,13 +146,12 @@ static void lpc_common_init(device_t dev)
|
|||
pci_write_config8(dev, 0x74, byte);
|
||||
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
|
||||
|
||||
setup_ioapic(dword);
|
||||
|
||||
setup_ioapic(dword, master);
|
||||
}
|
||||
|
||||
static void lpc_slave_init(device_t dev)
|
||||
{
|
||||
lpc_common_init(dev);
|
||||
lpc_common_init(dev, 0);
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
|
@ -166,13 +172,12 @@ static void lpc_init(device_t dev)
|
|||
int on;
|
||||
int nmi_option;
|
||||
|
||||
lpc_common_init(dev);
|
||||
lpc_common_init(dev, 1);
|
||||
|
||||
#if 0
|
||||
/* posted memory write enable */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
pci_write_config8(dev, 0x46, byte | (1<<0));
|
||||
|
||||
#endif
|
||||
/* power after power fail */
|
||||
|
||||
|
|
@ -198,7 +203,7 @@ static void lpc_init(device_t dev)
|
|||
dword = inl(pm10_bar + 0x10);
|
||||
on = 8-on;
|
||||
printk_debug("Throttling CPU %2d.%1.1d percent.\n",
|
||||
(on*12)+(on>>1),(on&1)*5);
|
||||
(on*12)+(on>>1),(on&1)*5);
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue