intel/common: CAR setup CQOS
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -254,6 +254,24 @@ car_nem:
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#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
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.global car_cqos
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car_cqos:
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/*
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* Create CBM_LEN_MASK based on CBM_LEN
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* Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0]
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*/
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mov $0x10, %eax
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mov $0x2, %ecx
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cpuid
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and $0x1F, %eax
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add $1, %al
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mov $1, %ebx
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mov %al, %cl
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shl %cl, %ebx
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sub $1, %ebx
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/* Store the CBM_LEN_MASK in mm3 for later use. */
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movd %ebx, %mm3
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/*
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* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
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* prefetchers slow down filling cache with rep stos in CQOS mode.
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@ -284,7 +302,7 @@ car_cqos:
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/* Set this mask for initial cache fill */
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mov $MSR_L2_QOS_MASK(0), %ecx
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rdmsr
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mov %bl, %al
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mov %ebx, %eax
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wrmsr
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/* Set CLOS selector to 0 */
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@ -297,8 +315,15 @@ car_cqos:
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mov $MSR_L2_QOS_MASK(1), %ecx
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rdmsr
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/* Invert bits that are to be used for cache */
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mov %bl, %al
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xor $~0, %al /* invert 8 bits */
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mov %ebx, %eax
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xor $~0, %eax /* invert 32 bits */
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/*
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* Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit
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* Mask Length.
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*/
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movd %mm3, %ebx
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and %ebx, %eax
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wrmsr
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post_code(0x26)
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