mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0

The TBT device can't be recognized after we re-plug it at DB type-c
port. Intel found that tbt_pcie_rp0 has mapping error after each
re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this
problem and take this as short term solution. Intel will implement
re-mapping mechanism in ACPI for long term solution.

BUG=b:230141802
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61429033dfe64d67916167bb901bdd8246db953e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/felwinter/overridetree.cb

@@ -181,7 +181,7 @@ chip soc/intel/alderlake
 				device generic 0 alias dptf_policy on end
 			end
 		end
-		device ref tbt_pcie_rp0 off end
+		device ref tbt_pcie_rp0 on end
 		device ref tbt_pcie_rp1 on
 			probe DB_USB USB4_KB8001
 		end