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sb/intel: Replace bad uses of `find_resource` 

The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.

Change-Id: I13c7ebeba2e5a896d46231b5e176e5470da97343
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Angel Pons 2021-11-03 13:07:14 +01:00 committed by Felix Held
parent 5065ad1f69
commit f32ae10f0d
17 changed files with 18 additions and 18 deletions
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2
src/southbridge/intel/bd82x6x/azalia.c
View File

@ -158,7 +158,7 @@ static void azalia_init(struct device *dev)
u32 codec_mask;
u32 reg32;
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/bd82x6x/me_common.c
View File

@ -336,7 +336,7 @@ int intel_mei_setup(struct device *dev)
struct mei_csr host;
/* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res || res->base == 0 || res->size == 0) {
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;

2
src/southbridge/intel/bd82x6x/smbus.c
View File

@ -19,7 +19,7 @@ static void pch_smbus_init(struct device *dev)
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
res = probe_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}

2
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -43,7 +43,7 @@ static void usb_ehci_init(struct device *dev)
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
reg32 = read32((void *)(uintptr_t)(res->base + 4));

2
src/southbridge/intel/i82801gx/azalia.c
View File

@ -186,7 +186,7 @@ static void azalia_init(struct device *dev)
// Docking not supported
pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/i82801gx/sata.c
View File

@ -130,7 +130,7 @@ static void sata_init(struct device *dev)
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5);
if (ahci_res != NULL)
/* write AHCI GHC_PI register */
write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);

2
src/southbridge/intel/i82801ix/azalia.c
View File

@ -179,7 +179,7 @@ static void azalia_init(struct device *dev)
/* Lock some R/WO bits by writing their current value. */
pci_update_config32(dev, 0x74, ~0, 0);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/i82801jx/azalia.c
View File

@ -179,7 +179,7 @@ static void azalia_init(struct device *dev)
/* Lock some R/WO bits by writing their current value. */
pci_update_config32(dev, 0x74, ~0, 0);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/ibexpeak/azalia.c
View File

@ -158,7 +158,7 @@ static void azalia_init(struct device *dev)
u32 reg32;
/* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/ibexpeak/me.c
View File

@ -395,7 +395,7 @@ static int intel_mei_setup(struct device *dev)
u16 reg16;
/* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res || res->base == 0 || res->size == 0) {
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;

2
src/southbridge/intel/ibexpeak/smbus.c
View File

@ -19,7 +19,7 @@ static void pch_smbus_init(struct device *dev)
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
res = probe_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}

2
src/southbridge/intel/ibexpeak/thermal.c
View File

@ -14,7 +14,7 @@ static void thermal_init(struct device *dev)
u8 *base;
printk(BIOS_DEBUG, "Thermal init start.\n");
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/ibexpeak/usb_ehci.c
View File

@ -36,7 +36,7 @@ static void usb_ehci_init(struct device *dev)
/* Enable writes to protected registers. */
pci_write_config8(dev, 0x80, access_cntl | 1);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
reg32 = read32((u32 *)(uintptr_t)(res->base + 4));

2
src/southbridge/intel/lynxpoint/azalia.c
View File

@ -101,7 +101,7 @@ static void azalia_init(struct device *dev)
u32 codec_mask;
/* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;

2
src/southbridge/intel/lynxpoint/me.c
View File

@ -670,7 +670,7 @@ static int intel_mei_setup(struct device *dev)
struct mei_csr host;
/* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!res || res->base == 0 || res->size == 0) {
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;

4
src/southbridge/intel/lynxpoint/serialio.c
View File

@ -166,10 +166,10 @@ static void serialio_init(struct device *dev)
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (!bar0)
return;
bar1 = find_resource(dev, PCI_BASE_ADDRESS_1);
bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1);
if (!bar1)
return;

2
src/southbridge/intel/lynxpoint/smbus.c
View File

@ -18,7 +18,7 @@ static void pch_smbus_init(struct device *dev)
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
res = probe_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
}