AMD binaryPI: Split romstage ram stack
Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -25,13 +25,9 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
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{
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{
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UINT32 heap = BIOS_HEAP_START_ADDRESS;
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UINT32 heap = BIOS_HEAP_START_ADDRESS;
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#if CONFIG_HAVE_ACPI_RESUME
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if (acpi_is_wakeup_s3())
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/* Both romstage and ramstage has this S3 detect. */
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heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH);
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if (acpi_get_sleep_type() == 3)
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heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
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(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
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/* himem_heap_base + high_stack_size */
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#endif
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return heap;
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return heap;
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}
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}
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@ -137,11 +137,12 @@ void restore_mtrr(void)
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#ifdef __PRE_RAM__
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#ifdef __PRE_RAM__
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static void move_stack_high_mem(void)
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static void move_stack_high_mem(void)
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{
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{
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void *high_stack;
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void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK);
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if (high_stack == NULL)
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halt();
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high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
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/* TODO: Make the switch with empty stack instead. */
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memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
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memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
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(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
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#ifdef __x86_64__
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#ifdef __x86_64__
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__asm__
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__asm__
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@ -31,4 +31,7 @@ void OemAgesaSaveMtrr (void);
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void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
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void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
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/* This covers node 0 only. */
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#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR)
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#endif
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#endif
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