intel/e7501: Remove unused northbridge code
No boards left in the tree for this northbridge. Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17281 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
8160a2f63d
commit
f338fa1f31
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@ -1,4 +0,0 @@
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config NORTHBRIDGE_INTEL_E7501
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bool
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select HAVE_DEBUG_RAM_SETUP
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select LATE_CBMEM_INIT
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@ -1,5 +0,0 @@
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7501),y)
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ramstage-y += northbridge.c
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endif
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@ -1,175 +0,0 @@
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/*
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* generic debug code, used by mainboard specific romstage.c
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*
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*/
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#if 1
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static void print_debug_pci_dev(unsigned dev)
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{
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
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(dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
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}
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static inline void print_pci_devices(void)
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{
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device_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0xff, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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printk(BIOS_DEBUG, "\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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for (i = 0; i < 256; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0)
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printk(BIOS_DEBUG, "\n%02x:",i);
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val = pci_read_config8(dev, i);
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printk(BIOS_DEBUG, " %02x", val);
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}
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printk(BIOS_DEBUG, "\n");
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}
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static inline void dump_pci_devices(void)
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{
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device_t dev;
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for (dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0xff, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static inline void dump_pci_devices_on_bus(unsigned busn)
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{
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device_t dev;
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for (dev = PCI_DEV(busn, 0, 0);
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dev <= PCI_DEV(busn, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static inline void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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printk(BIOS_DEBUG, "\n");
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for (i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
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for (j = 0; j < 128; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0)
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printk(BIOS_DEBUG, "\n%02x: ", j);
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status = smbus_read_byte(device, j);
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if (status < 0) {
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break;
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}
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byte = status & 0xff;
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printk(BIOS_DEBUG, "%02x ", byte);
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}
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printk(BIOS_DEBUG, "\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
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for (j = 0; j < 128; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0)
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printk(BIOS_DEBUG, "\n%02x: ", j);
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status = smbus_read_byte(device, j);
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if (status < 0) {
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break;
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}
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byte = status & 0xff;
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printk(BIOS_DEBUG, "%02x ", byte);
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}
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printk(BIOS_DEBUG, "\n");
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}
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}
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}
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static inline void dump_smbus_registers(void)
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{
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unsigned device;
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printk(BIOS_DEBUG, "\n");
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for (device = 1; device < 0x80; device++) {
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int j;
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if ( smbus_read_byte(device, 0) < 0 ) continue;
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printk(BIOS_DEBUG, "smbus: %02x", device);
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for (j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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status = smbus_read_byte(device, j);
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if (status < 0) {
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break;
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}
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if ((j & 0xf) == 0)
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printk(BIOS_DEBUG, "\n%02x: ",j);
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byte = status & 0xff;
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printk(BIOS_DEBUG, "%02x ", byte);
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}
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printk(BIOS_DEBUG, "\n");
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}
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}
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static inline void dump_io_resources(unsigned port)
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{
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int i;
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printk(BIOS_DEBUG, "%04x:\n", port);
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for (i = 0; i < 256; i++) {
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uint8_t val;
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if ((i & 0x0f) == 0)
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printk(BIOS_DEBUG, "%02x:", i);
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val = inb(port);
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printk(BIOS_DEBUG, " %02x",val);
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if ((i & 0x0f) == 0x0f) {
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printk(BIOS_DEBUG, "\n");
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}
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port++;
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}
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}
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static inline void dump_mem(unsigned start, unsigned end)
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{
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unsigned i;
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printk(BIOS_DEBUG, "dump_mem:");
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for (i = start; i < end; i++) {
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if ((i & 0xf)==0)
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printk(BIOS_DEBUG, "\n%08x:", i);
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printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
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}
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printk(BIOS_DEBUG, "\n");
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}
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#endif
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@ -1,80 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* e7501.h: PCI configuration space for the Intel E7501 memory controller
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*/
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#ifndef NORTHBRIDGE_INTEL_E7501_E7501_H
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#define NORTHBRIDGE_INTEL_E7501_E7501_H
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/************ D0:F0 ************/
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// Register offsets
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#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */
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#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
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#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
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#define DRB_ROW_1 0x61
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#define DRB_ROW_2 0x62
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#define DRB_ROW_3 0x63
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#define DRB_ROW_4 0x64
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#define DRB_ROW_5 0x65
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#define DRB_ROW_6 0x66
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#define DRB_ROW_7 0x67
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#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */
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#define DRT 0x78 /* DRAM Timing register, 32 bit */
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#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */
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#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
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#define CKDIS 0x8C /* Clock disable register, 8 bit */
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#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */
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#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */
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#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */
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#define SKPD 0xDE /* Scratchpad register, 16 bit */
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#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */
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// CAS# Latency bits in the DRAM Timing (DRT) register
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#define DRT_CAS_2_5 (0<<4)
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#define DRT_CAS_2_0 (1<<4)
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#define DRT_CAS_MASK (3<<4)
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// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
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#define RAM_COMMAND_NOP (1<<4)
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#define RAM_COMMAND_PRECHARGE (2<<4)
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#define RAM_COMMAND_MRS (3<<4)
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#define RAM_COMMAND_EMRS (4<<4)
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#define RAM_COMMAND_CBR (6<<4)
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#define RAM_COMMAND_NORMAL (7<<4)
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// RCOMP Memory Map offsets
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// Conjecture based on apparent similarity between E7501 and 855PM
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// Intel doc. 252613-003 describes these for 855PM
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#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */
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#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */
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#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */
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#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */
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#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */
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#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */
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/************ D0:F1 ************/
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// Register offsets
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#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */
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#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */
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#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */
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#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */
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#endif /* NORTHBRIDGE_INTEL_E7501_E7501_H */
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@ -1,140 +0,0 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cbmem.h>
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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/* Just a dummy */
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return current;
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}
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#endif
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static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(dev->link_list);
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mc_dev = dev->link_list->children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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int idx;
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 64MB
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* i.e. 1 means 64MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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}
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/* Write the RAM configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, remaplimit_r);
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > 4*1024*1024) {
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ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, idx++, remapbasek,
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(remaplimitk + 64*1024) - remapbasek);
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}
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set_top_of_ram(tolmk * 1024);
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}
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_e7501_ops = {
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CHIP_NAME("Intel E7501 Northbridge")
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.enable_dev = enable_dev,
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};
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File diff suppressed because it is too large
Load Diff
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@ -1,20 +0,0 @@
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#ifndef RAMINIT_H
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#define RAMINIT_H
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#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
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#define MAX_NUM_CHANNELS 2
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#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
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struct mem_controller {
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device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
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// SMBus addresses of DIMM slots for each channel,
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// in order from closest to MCH to furthest away
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// 0 == not present
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uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
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uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
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};
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void sdram_initialize(int controllers, const struct mem_controller *ctrl);
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#endif /* RAMINIT_H */
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@ -1,18 +0,0 @@
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/* Convert to C by yhlu */
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#define MCH_DRC 0x7c
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#define DRC_DONE (1 << 29)
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/* If I have already booted once skip a bunch of initialization */
|
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/* To see if I have already booted I check to see if memory
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* has been enabled.
|
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*/
|
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static int bios_reset_detected(void) {
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uint32_t dword;
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|
||||
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
|
||||
|
||||
if ( (dword & DRC_DONE) != 0 ) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue