soc/intel/common/cse: Add support to get CSME timestamps
This command retrieves a set of boot performance timestamps CSME collected during the platform's last boot flow. BUG=b:182575295 TEST=Verify CSME timestamps after S3 and boot. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Bora Guvendik
Felix Held
parent
03b1d3ef48
commit
f33c9bf79a
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@ -2,6 +2,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
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ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
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ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
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@ -127,6 +127,38 @@ struct get_bp_info_rsp {
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struct cse_bp_info bp_info;
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} __packed;
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bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp)
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{
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struct cse_boot_perf_req {
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struct mkhi_hdr hdr;
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uint32_t reserved;
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} __packed;
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struct cse_boot_perf_req req = {
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.hdr.group_id = MKHI_GROUP_ID_BUP_COMMON,
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.hdr.command = MKHI_BUP_COMMON_GET_BOOT_PERF_DATA,
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.reserved = 0,
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};
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size_t resp_size = sizeof(struct cse_boot_perf_rsp);
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if (!heci_send_receive(&req, sizeof(req), boot_perf_rsp, &resp_size,
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HECI_MKHI_ADDR)) {
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printk(BIOS_ERR, "cse_lite: Could not get boot performance data\n");
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return false;
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}
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if (boot_perf_rsp->hdr.result) {
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printk(BIOS_ERR, "cse_lite: Get boot performance data resp failed: %d\n",
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boot_perf_rsp->hdr.result);
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return false;
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}
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return true;
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}
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static uint8_t cse_get_current_bp(const struct cse_bp_info *cse_bp_info)
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{
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return cse_bp_info->current_bp;
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@ -41,6 +41,9 @@
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#define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d
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#define MKHI_BUP_COMMON_DATA_CLEAR 0x20
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/* Get boot performance command id */
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#define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA 0x8
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/* ME Current Working States */
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#define ME_HFS1_CWS_NORMAL 0x5
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@ -60,6 +63,9 @@
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#define ME_HFS3_FW_SKU_CORPORATE 0x3
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#define ME_HFS3_FW_SKU_LITE 0x5
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/* Number of cse boot performance data */
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#define NUM_CSE_BOOT_PERF_DATA 64
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/* HFSTS register offsets in PCI config space */
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enum {
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PCI_ME_HFSTS1 = 0x40,
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@ -163,6 +169,130 @@ enum csme_failure_reason {
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CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18,
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};
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/* Boot performance data */
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enum cse_boot_perf_data {
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/* CSME ROM start execution */
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PERF_DATA_CSME_ROM_START = 0,
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/* EC Boot Load Done (CSME ROM starts main execution) */
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PERF_DATA_EC_BOOT_LOAD_DONE = 1,
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/* CSME ROM completed execution / CSME RBE started */
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PERF_DATA_CSME_ROM_COMPLETED = 2,
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/* CSME got ESE Init Done indication from ESE */
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PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3,
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/* CSME RBE start PMC patch/es loading */
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PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4,
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/* CSME RBE completed PMC patch/es loading */
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PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5,
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/* CSME RBE set "Boot Stall Done" indication to PMC */
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PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6,
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/* CSME start poll for PMC PPS register */
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PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7,
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/* PMC set PPS */
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PERF_DATA_PMC_SET_PPS = 8,
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/* CSME BUP start running */
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PERF_DATA_CSME_BUP_START = 9,
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/* CSME set "Host Boot Prep Done" indication to PMC */
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PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10,
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/* CSME starts PHYs loading */
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PERF_DATA_CSME_PHY_LOADING_START = 11,
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/* CSME completed PHYs loading */
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PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12,
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/* PMC indicated CSME that xxPWRGOOD was asserted */
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PERF_DATA_PMC_PWRGOOD_ASSERTED = 13,
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/* PMC indicated CSME that SYS_PWROK was asserted */
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PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14,
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/* PMC sent "CPU_BOOT_CONFIG" start message to CSME */
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PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15,
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/* CSME sent "CPU_BOOT_CONFIG" done message to PMC */
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PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW = 16,
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/* PMC indicated CSME that xxPLTRST was de-asserted */
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PERF_DATA_PMC_PLTRST_DEASSERTED = 17,
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/* PMC indicated CSME that TCO_S0 was asserted */
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PERF_DATA_PMC_TC0_S0_ASSERTED = 18,
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/* PMC sent "Core Reset Done Ack - Sent" message to CSME */
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PERF_DATA_PMC_SENT_CRDA = 19,
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/* ACM Active indication - ACM started its execution */
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PERF_DATA_ACM_START = 20,
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/* ACM Done indication - ACM completed execution */
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PERF_DATA_ACM_DONE = 21,
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/* BIOS sent DRAM Init Done message */
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PERF_DATA_BIOS_DRAM_INIT_DONE = 22,
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/* CSME sent DRAM Init Done message back to BIOS */
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PERF_DATA_CSME_DRAM_INIT_DONE = 23,
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/* CSME completed loading TCSS */
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PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24,
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/* CSME started loading ISH Bringup module */
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PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25,
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/* CSME completed loading ISH Bringup module */
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PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26,
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/* CSME started loading ISH Main module */
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PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27,
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/* CSME completed loading Main module */
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PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28,
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/* BIOS sent "End Of Post" message to CSME */
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PERF_DATA_BIOS_END_OF_POST = 29,
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/* CSME sent "End Of Post" ack message back to BIOS */
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PERF_DATA_CSME_END_OF_POST = 30,
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/* BIOS sent "Core BIOS Done" message to CSME */
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PERF_DATA_BIOS_BIOS_CORE_DONE = 31,
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/* CSME sent "Core BIOS Done" ack message back to BIOS */
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PERF_DATA_CSME_BIOS_CORE_DONE = 32,
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/* CSME reached Firmware Init Done */
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PERF_DATA_CSME_GW_INIT_DONE = 33,
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/* 34 - 62 Reserved */
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/* Timestamp when CSME responded to BupGetBootData message itself */
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PERF_DATA_CSME_GET_PERF_RESPONSE = 63,
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};
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/* CSE boot performance data */
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struct cse_boot_perf_rsp {
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struct mkhi_hdr hdr;
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/* Data version */
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uint32_t version;
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/* Data length in DWORDs, represents number of valid elements in timestamp array */
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uint32_t num_valid_timestamps;
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/* Boot performance data */
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uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA];
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} __packed;
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/* set up device for use in early boot enviroument with temp bar */
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void heci_init(uintptr_t bar);
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@ -349,4 +479,11 @@ bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_st
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* Returns true if cse sub-parition update is required otherwise false.
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*/
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bool skip_cse_sub_part_update(void);
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/*
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* This command retrieves a set of boot performance timestamps CSME collected during
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* the last platform boot flow.
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*/
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bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf);
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#endif // SOC_INTEL_COMMON_CSE_H
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