mainboard/pine64/rockpro64: Add initial ROCKPro64 support

This adds initial support for the Pine64 ROCKPro64 board.

The ROCKPro64 (http://pine64.org/rockpro64) is a SBC using the
RK3399 SoC with up to 4GB LPDDR4.

So far only the bootblock part works, the romstage starts to execute,
though.

For ramstage to work we'll need to port some of the changes required
for LPDDR4 vs LPDDR3. This will be addressed in follow up changes.

UART2 on the PI-2 connector can be used as a coreboot console.

  GND is pin 6
  TXD is pin 8
  RXD is pin 10

Flashing:
  I used an OpenWRT nightly for the ROCKPro64 and its builtin tool.

  $ mtd write coreboot.rom /dev/mtd0

Recovering from a bad flash:
  To recover from a bad flash bridging pins 23 and 25 on the PI-2
  connector will make the board boot from SD card.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I47d0031fff8ee10b11ad74935eaeb05f1f7eb4b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50625
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Moritz Fischer 2021-02-12 15:39:38 -08:00 committed by ron minnich
parent b2d633db07
commit f34bdf8c5e
10 changed files with 134 additions and 0 deletions

View File

@ -0,0 +1,17 @@
## SPDX-License-Identifier: GPL-2.0-only
if VENDOR_PINE64
choice
prompt "Mainboard model"
source "src/mainboard/pine64/*/Kconfig.name"
endchoice
source "src/mainboard/pine64/*/Kconfig"
config MAINBOARD_VENDOR
default "Pine64"
endif # VENDOR_PINE64

View File

@ -0,0 +1,2 @@
config VENDOR_PINE64
bool "Pine64"

View File

@ -0,0 +1,36 @@
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_PINE64_ROCKPRO64
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select COMMON_CBFS_SPI_WRAPPER
select SOC_ROCKCHIP_RK3399
select SPI_FLASH
select SPI_FLASH_GIGADEVICE
config MAINBOARD_DIR
string
default "pine64/rockpro64"
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 1
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xFF1A0000
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config DEVICETREE
string
default "devicetree.cb" if BOARD_PINE64_ROCKPRO64
config MAINBOARD_PART_NUMBER
string
default "ROCKPro64" if BOARD_PINE64_ROCKPRO64
endif # BOARD_PINE64_ROCKPRO64

View File

@ -0,0 +1,2 @@
config BOARD_PINE64_ROCKPRO64
bool "ROCKPro64"

View File

@ -0,0 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only
all-y += reset.c
bootblock-y += bootblock.c

View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __COREBOOT_SRC_MAINBOARD_PINE64_ROCKPRO64_BOARD_H
#define __COREBOOT_SRC_MAINBOARD_PINE64_ROCKPRO64_BOARD_H
#include <gpio.h>
#define GPIO_RESET GPIO(1, A, 6)
#endif /* ! __COREBOOT_SRC_MAINBOARD_PINE64_ROCKPRO64_BOARD_H */

View File

@ -0,0 +1,6 @@
Vendor name: Pine64
Board name: ROCKPro64
Category: sbc
ROM protocol: SPI
ROM socketed: n
Flashrom support: n

View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <bootblock_common.h>
#include <soc/grf.h>
#include <gpio.h>
#include <soc/spi.h>
void bootblock_mainboard_early_init(void)
{
if (CONFIG(CONSOLE_SERIAL)) {
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
"CONSOLE_SERIAL_UART should be UART2");
/* iomux: select gpio4c[4:3] as uart2 dbg port */
write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
/* grf soc_con7[11:10] use for uart2 select */
write32(&rk3399_grf->soc_con7, UART2C_SEL);
}
}
static void configure_spi_flash(void)
{
gpio_input(GPIO(1, A, 7)); /* SPI1_MISO remove pull-up */
gpio_input(GPIO(1, B, 0)); /* SPI1_MOSI remove pull-up */
gpio_input(GPIO(1, B, 1)); /* SPI1_CLK remove pull-up */
gpio_input(GPIO(1, B, 2)); /* SPI1_CS remove pull-up */
rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33 * MHz);
rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);
write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
}
void bootblock_mainboard_init(void)
{
configure_spi_flash();
}

View File

@ -0,0 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only
chip soc/rockchip/rk3399
device cpu_cluster 0 on end
end

View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <gpio.h>
#include <reset.h>
#include "board.h"
void do_board_reset(void)
{
gpio_output(GPIO_RESET, 1);
}