Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear on if the NM10 has any other PCI IDs. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -171,6 +171,7 @@ int print_gpios(struct pci_dev *sb)
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gpio_registers = ich9_gpio_registers;
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size = ARRAY_SIZE(ich9_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich8_gpio_registers;
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@ -180,6 +181,7 @@ int print_gpios(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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case PCI_DEVICE_ID_INTEL_NM10:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich7_gpio_registers;
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size = ARRAY_SIZE(ich7_gpio_registers);
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@ -61,6 +61,8 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
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@ -43,6 +43,8 @@
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_NM10 0x27bc
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#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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@ -477,6 +477,7 @@ int print_pmbase(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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case PCI_DEVICE_ID_INTEL_NM10:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich7_pm_registers;
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size = ARRAY_SIZE(ich7_pm_registers);
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@ -491,6 +492,7 @@ int print_pmbase(struct pci_dev *sb)
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pm_registers = ich9_pm_registers;
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size = ARRAY_SIZE(ich9_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich8_pm_registers;
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@ -43,6 +43,8 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH9M:
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case PCI_DEVICE_ID_INTEL_ICH9ME:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_NM10:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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