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mainboard/intel/cannonlake_rvp: Enable hardware P state control 

This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.

Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Vaibhav Shankar 2017-10-16 10:16:27 -07:00 committed by Aaron Durbin
parent f46a9a0d3a
commit f36ed21c57
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -67,6 +67,9 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5" register "PcieClkSrcClkReq[5]" = "5"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device

3
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
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@ -65,6 +65,9 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5" register "PcieClkSrcClkReq[5]" = "5"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device