soc/medaitek/mt8195: adjust USB phy shift value
There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -130,9 +130,13 @@ struct sif_u2_phy_com {
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check_member(sif_u2_phy_com, u2phydtm0, 0x68);
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check_member(sif_u2_phy_com, u2phydtm0, 0x68);
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struct sif_u3phyd {
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struct sif_u3phyd {
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u32 reserved0[23];
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u32 reserved0[4];
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u32 phyd_cal0;
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u32 phyd_cal1;
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u32 reserved1[15];
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u32 phyd_reserved;
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u32 phyd_cdr1;
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u32 phyd_cdr1;
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u32 reserved1[40];
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u32 reserved2[41];
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};
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};
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struct sif_u3phya {
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struct sif_u3phya {
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@ -155,6 +159,7 @@ struct sif_u3phya_da {
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* SOCs will not need it.
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* SOCs will not need it.
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*/
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*/
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void mtk_usb_prepare(void);
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void mtk_usb_prepare(void);
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void mtk_usb_adjust_phy_shift(void);
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void setup_usb_host(void);
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void setup_usb_host(void);
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@ -140,7 +140,15 @@ static inline void ssusb_soft_reset(void)
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clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
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clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
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}
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}
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__weak void mtk_usb_prepare(void) { /* do nothing */ }
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__weak void mtk_usb_prepare(void)
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{
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/* do nothing */
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}
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__weak void mtk_usb_adjust_phy_shift(void)
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{
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/* do nothing */
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}
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void setup_usb_host(void)
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void setup_usb_host(void)
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{
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{
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@ -153,5 +161,6 @@ void setup_usb_host(void)
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return;
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return;
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}
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}
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u3phy_power_on();
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u3phy_power_on();
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mtk_usb_adjust_phy_shift();
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u3p_msg("phy power-on done.\n");
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u3p_msg("phy power-on done.\n");
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}
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}
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@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya, 0x800);
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check_member(ssusb_sif_port, u3phya_da, 0x900);
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check_member(ssusb_sif_port, u3phya_da, 0x900);
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check_member(ssusb_sif_port, reserved2, 0xa00);
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check_member(ssusb_sif_port, reserved2, 0xa00);
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#define USB_PORT_NUMBER 1
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DEFINE_BIT(AUTO_LOAD_DIS, 12)
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DEFINE_BITFIELD(TX_IMP_CAL, 28, 24)
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DEFINE_BIT(TX_IMP_CAL_EN, 31)
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DEFINE_BITFIELD(RX_IMP_CAL, 28, 24)
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DEFINE_BIT(RX_IMP_CAL_EN, 31)
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DEFINE_BITFIELD(INTR_CAL, 15, 10)
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#define TX_IMP_MASK 0x1F
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#define TX_IMP_SHIFT 0
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#define RX_IMP_MASK 0x3E0
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#define RX_IMP_SHIFT 5
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#define INTR_CAL_MASK 0xFC00
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#define INTR_CAL_SHIFT 10
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#define USB_PHY_SETTING_REG 0x11C10184
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#define USB_PORT_NUMBER 1
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#endif
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#endif
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@ -10,3 +10,31 @@ void mtk_usb_prepare(void)
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setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
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setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
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setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
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setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
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}
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}
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void mtk_usb_adjust_phy_shift(void)
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{
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u32 phy_set_val, write_val;
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struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE);
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SET32_BITFIELDS(&phy->u3phyd.phyd_reserved,
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AUTO_LOAD_DIS, 1);
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phy_set_val = read32((void *)USB_PHY_SETTING_REG);
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/* TX imp */
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write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT;
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SET32_BITFIELDS(&phy->u3phyd.phyd_cal0,
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TX_IMP_CAL, write_val,
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TX_IMP_CAL_EN, 1);
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/* RX imp */
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write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT;
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SET32_BITFIELDS(&phy->u3phyd.phyd_cal1,
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RX_IMP_CAL, write_val,
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RX_IMP_CAL_EN, 1);
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/* Intr_cal */
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write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT;
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SET32_BITFIELDS(&phy->u3phya.phya_reg0,
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INTR_CAL, write_val);
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}
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