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In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o 

space offset 0x1000, and later is the acpi registers also mapped at 0x1000. 
This patch fixes this behavior. Closes #44

Signed-off-by: <chn@virtutech.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
chn 2006-12-14 00:43:50 +00:00 committed by Stefan Reinauer
parent a522df039b
commit f3938bbbbf
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/intel/i82801ca/i82801ca_lpc.c
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@ -121,8 +121,8 @@ void i82801ca_1f0_misc(struct device *dev)
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
pci_write_config16(dev, PCI_COMMAND, 0x014f);
// Set ACPI base address to 0x1000 (I/O space)
pci_write_config32(dev, PMBASE, 0x00001001);
// Set ACPI base address to 0x1100 (I/O space)
pci_write_config32(dev, PMBASE, 0x00001101);
// Enable ACPI I/O and power management
pci_write_config8(dev, ACPI_CNTL, 0x10);