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soc/intel/alderlake: Drop 100ms delay and do not poll Link Active 

Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.

BUG=None
TEST=Built Alderlake coreboot image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2021-03-02 09:31:15 -08:00 committed by Patrick Georgi
parent 80273918d5
commit f3a8bf13cb
1 changed files with 0 additions and 14 deletions
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14
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
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@ -140,18 +140,6 @@ Method (D3CX, 0, Serialized)
Local1 = L23R Local1 = L23R
} }
STAT = 0x1 STAT = 0x1
/* Wait for LA = 1 */
Local0 = 0
Local1 = LASX
While (Local1 == 0) {
If (Local0 > 20) {
Break
}
Sleep(5)
Local0++
Local1 = LASX
}
} }
/* /*
@ -192,8 +180,6 @@ Method (_PS0, 0, Serialized)
If (PMEX == 1) { If (PMEX == 1) {
PMEX = 0 /* Disable Power Management SCI */ PMEX = 0 /* Disable Power Management SCI */
} }
Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */
} }
Method (_PS3, 0, Serialized) Method (_PS3, 0, Serialized)