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rockchip/rk3399: Directly access variables in sdram.c 

This simplifies some of the code with better variable declaractions
which removes a lot of line continuations. Instead of declaring a
pointer to the container of the needed struct or array, this retrieves
a pointer to the struct or array instead.

BRANCH=none
BUG=none
TEST=check that gru and kevin still build and boot properly followed
by running "stressapptest -M 1024 -s 1000" and making sure it passes

Change-Id: I34a9be0f35981c03a6b0c27a870981a5f69cecc0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5c17449fcdfbe83ec75a3a006aaf7393c66006b7
Original-Change-Id: If4e386d4029f17d811fa3ce83e5be89e661a7b11
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354162
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15655
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Derek Basehore 2016-06-23 14:28:12 -07:00 committed by Martin Roth
parent 1dd0bc0f60
commit f3b3ccfe73
1 changed files with 224 additions and 313 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

523
src/soc/rockchip/rk3399/sdram.c
View File

@ -118,90 +118,71 @@ static void ddr_move_to_access_state(u32 channel)
static void phy_dll_bypass_set(u32 channel,
struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
{
u32 *denali_phy = ddr_publ_regs->denali_phy;
if (freq <= 125*MHz) {
/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
setbits_le32(&ddr_publ_regs->denali_phy[86],
(0x3 << 2) << 8);
setbits_le32(&ddr_publ_regs->denali_phy[214],
(0x3 << 2) << 8);
setbits_le32(&ddr_publ_regs->denali_phy[342],
(0x3 << 2) << 8);
setbits_le32(&ddr_publ_regs->denali_phy[470],
(0x3 << 2) << 8);
setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
setbits_le32(&ddr_publ_regs->denali_phy[547],
(0x3 << 2) << 16);
setbits_le32(&ddr_publ_regs->denali_phy[675],
(0x3 << 2) << 16);
setbits_le32(&ddr_publ_regs->denali_phy[803],
(0x3 << 2) << 16);
setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
} else {
/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
clrbits_le32(&ddr_publ_regs->denali_phy[86],
(0x3 << 2) << 8);
clrbits_le32(&ddr_publ_regs->denali_phy[214],
(0x3 << 2) << 8);
clrbits_le32(&ddr_publ_regs->denali_phy[342],
(0x3 << 2) << 8);
clrbits_le32(&ddr_publ_regs->denali_phy[470],
(0x3 << 2) << 8);
clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
clrbits_le32(&ddr_publ_regs->denali_phy[547],
(0x3 << 2) << 16);
clrbits_le32(&ddr_publ_regs->denali_phy[675],
(0x3 << 2) << 16);
clrbits_le32(&ddr_publ_regs->denali_phy[803],
(0x3 << 2) << 16);
clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
}
}
static void set_memory_map(u32 channel,
const struct rk3399_sdram_params *sdram_params)
{
struct rk3399_ddr_pctl_regs *ddr_pctl_regs =
rk3399_ddr_pctl[channel];
const struct rk3399_sdram_channel *sdram_ch =
&sdram_params->ch[channel];
u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
u32 cs_map;
u32 reduc;
struct rk3399_ddr_pi_regs *ddr_pi_regs =
rk3399_ddr_pi[channel];
cs_map = (sdram_params->ch[channel].rank > 1) ? 3 : 1;
reduc = (sdram_params->ch[channel].bw == 2) ? 0 : 1;
cs_map = (sdram_ch->rank > 1) ? 3 : 1;
reduc = (sdram_ch->bw == 2) ? 0 : 1;
clrsetbits_le32(&ddr_pctl_regs->denali_ctl[191], 0xF,
(12 - sdram_params->ch[channel].col));
clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
((3 - sdram_ch->bk) << 16) |
((16 - sdram_ch->cs0_row) << 24));
clrsetbits_le32(&ddr_pctl_regs->denali_ctl[190],
(0x3 << 16) | (0x7 << 24),
((3 - sdram_params->ch[channel].bk) << 16) |
((16 - sdram_params->ch[channel].cs0_row) << 24));
clrsetbits_le32(&ddr_pctl_regs->denali_ctl[196],
0x3 | (1 << 16), cs_map | (reduc << 16));
clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
cs_map | (reduc << 16));
/* PI_199 PI_COL_DIFF:RW:0:4 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[199],
0xF, (12 - sdram_params->ch[channel].col));
clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[155],
(0x3 << 16) | (0x7 << 24),
((3 - sdram_params->ch[channel].bk) << 16) |
((16 - sdram_params->ch[channel].cs0_row) << 24));
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
((3 - sdram_ch->bk) << 16) |
((16 - sdram_ch->cs0_row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[41],
0xf << 24, cs_map << 24);
if ((sdram_params->ch[channel].rank == 1) &&
(sdram_params->dramtype == DDR3))
write32(&ddr_pi_regs->denali_pi[34], 0x2EC7FFFF);
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3))
write32(&denali_pi[34], 0x2EC7FFFF);
}
static void set_ds_odt(u32 channel,
const struct rk3399_sdram_params *sdram_params)
{
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
@ -250,90 +231,90 @@ static void set_ds_odt(u32 channel,
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
/*
* phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
* sets termination values for read/idle cycles and drive strength
* for write cycles for DQS
*/
clrsetbits_le32(&ddr_publ_regs->denali_phy[7], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[135], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[263], 0xffffff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[391], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
reg_value = tsel_wr_select_n | (tsel_wr_select_p << 0x4);
clrsetbits_le32(&ddr_publ_regs->denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff, reg_value);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff, reg_value);
clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0xff, reg_value);
clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0xff, reg_value);
clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0xff, reg_value);
clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0xff, reg_value);
clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0xff,
clrsetbits_le32(&denali_phy[924], 0xff,
tsel_wr_select_n | (tsel_wr_select_p << 4));
clrsetbits_le32(&ddr_publ_regs->denali_phy[925], 0xff,
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
/* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
<< 16;
clrsetbits_le32(&ddr_publ_regs->denali_phy[5], 0x7 << 16, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[133], 0x7 << 16, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[261], 0x7 << 16, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[389], 0x7 << 16, reg_value);
clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
/* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
<< 24;
clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0x7 << 24, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0x7 << 24, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0x7 << 24, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0x7 << 24, reg_value);
clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
/* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
reg_value = tsel_wr_en << 8;
clrsetbits_le32(&ddr_publ_regs->denali_phy[518], 0x1 << 8, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[646], 0x1 << 8, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[774], 0x1 << 8, reg_value);
clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
/* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
reg_value = tsel_wr_en << 17;
clrsetbits_le32((&ddr_publ_regs->denali_phy[933]), 0x1 << 17,
reg_value);
clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
/*
* pad_rst/cke/cs/clk_term tsel 1bits
* DENALI_PHY_938/936/940/934 offset_17
*/
clrsetbits_le32(&ddr_publ_regs->denali_phy[938], 0x1 << 17, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[936], 0x1 << 17, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[940], 0x1 << 17, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[934], 0x1 << 17, reg_value);
clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[930], 0x1 << 17, reg_value);
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
}
static void phy_io_config(u32 channel,
const struct rk3399_sdram_params *sdram_params)
{
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 vref_mode, vref_value;
u32 mode_sel = 0;
u32 speed;
@ -352,18 +333,15 @@ static void phy_io_config(u32 channel,
reg_value = (vref_mode << 9) | (0x1 << 8) | vref_value;
/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[913], 0xfff << 8,
reg_value << 8);
clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[914], 0xfff, reg_value);
clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[914], 0xfff << 16,
reg_value << 16);
clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff, reg_value);
clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff << 16,
reg_value << 16);
clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
if (sdram_params->dramtype == LPDDR4)
mode_sel = 0x6;
@ -373,29 +351,21 @@ static void phy_io_config(u32 channel,
mode_sel = 0x1;
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0x7 << 15,
mode_sel << 15);
clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
/* PHY_926 PHY_PAD_DATA_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x7 << 6,
mode_sel << 6);
clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
/* PHY_927 PHY_PAD_DQS_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x7 << 6,
mode_sel << 6);
clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
/* PHY_928 PHY_PAD_ADDR_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[928], 0x7 << 14,
mode_sel << 14);
clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
/* PHY_929 PHY_PAD_CLK_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0x7 << 14,
mode_sel << 14);
clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
/* PHY_935 PHY_PAD_CKE_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0x7 << 14,
mode_sel << 14);
clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
/* PHY_937 PHY_PAD_RST_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0x7 << 14,
mode_sel << 14);
clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x7 << 14,
mode_sel << 14);
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
if (sdram_params->ddr_freq < 400 * MHz)
speed = 0x0;
@ -407,38 +377,31 @@ static void phy_io_config(u32 channel,
die("Halting: Unknown DRAM speed.\n");
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0x3 << 21,
speed << 21);
clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21);
/* PHY_926 PHY_PAD_DATA_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x3 << 9,
speed << 9);
clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9);
/* PHY_927 PHY_PAD_DQS_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x3 << 9,
speed << 9);
clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9);
/* PHY_928 PHY_PAD_ADDR_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[928], 0x3 << 17,
speed << 17);
clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17);
/* PHY_929 PHY_PAD_CLK_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0x3 << 17,
speed << 17);
clrsetbits_le32(&denali_phy[929], 0x3 << 17, mode_sel << 17);
/* PHY_935 PHY_PAD_CKE_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0x3 << 17,
speed << 17);
clrsetbits_le32(&denali_phy[935], 0x3 << 17, mode_sel << 17);
/* PHY_937 PHY_PAD_RST_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0x3 << 17,
speed << 17);
clrsetbits_le32(&denali_phy[937], 0x3 << 17, mode_sel << 17);
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x3 << 17,
speed << 17);
clrsetbits_le32(&denali_phy[939], 0x3 << 17, mode_sel << 17);
}
static void pctl_cfg(u32 channel,
const struct rk3399_sdram_params *sdram_params)
{
struct rk3399_ddr_pctl_regs *ddr_pctl_regs = rk3399_ddr_pctl[channel];
struct rk3399_ddr_pi_regs *ddr_pi_regs = rk3399_ddr_pi[channel];
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 *params_ctl = (u32 *)sdram_params->pctl_regs.denali_ctl;
u32 *params_phy = (u32 *)sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
u32 pwrup_srefresh_exit;
@ -446,35 +409,30 @@ static void pctl_cfg(u32 channel,
* work around controller bug:
* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
*/
copy_to_reg(&ddr_pctl_regs->denali_ctl[1],
(u32 *)&sdram_params->pctl_regs.denali_ctl[1],
copy_to_reg(&denali_ctl[1], &params_ctl[1],
sizeof(struct rk3399_ddr_pctl_regs) - 4);
write32(&ddr_pctl_regs->denali_ctl[0],
sdram_params->pctl_regs.denali_ctl[0]);
copy_to_reg((u32 *)ddr_pi_regs,
(u32 *)&sdram_params->pi_regs.denali_pi[0],
write32(&denali_ctl[0], params_ctl[0]);
copy_to_reg(denali_pi, (u32 *)&sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
/* rank count need to set for init */
set_memory_map(channel, sdram_params);
write32(&ddr_publ_regs->denali_phy[910], 0x6400);
write32(&ddr_publ_regs->denali_phy[911], 0x01221102);
write32(&ddr_publ_regs->denali_phy[912], 0x0);
pwrup_srefresh_exit = read32(&ddr_pctl_regs->denali_ctl[68]) &
PWRUP_SREFRESH_EXIT;
clrbits_le32(&ddr_pctl_regs->denali_ctl[68], PWRUP_SREFRESH_EXIT);
write32(&denali_phy[910], 0x6400);
write32(&denali_phy[911], 0x01221102);
write32(&denali_phy[912], 0x0);
pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
clrsetbits_le32(&ddr_publ_regs->denali_phy[957],
0x3 << 24, 1 << 24);
clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
setbits_le32(&ddr_pi_regs->denali_pi[0], START);
setbits_le32(&ddr_pctl_regs->denali_ctl[0], START);
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
while (1) {
tmp = read32(&ddr_publ_regs->denali_phy[920]);
tmp1 = read32(&ddr_publ_regs->denali_phy[921]);
tmp2 = read32(&ddr_publ_regs->denali_phy[922]);
tmp = read32(&denali_phy[920]);
tmp1 = read32(&denali_phy[921]);
tmp2 = read32(&denali_phy[922]);
if ((((tmp >> 16) & 0x1) == 0x1) &&
(((tmp1 >> 16) & 0x1) == 0x1) &&
(((tmp1 >> 0) & 0x1) == 0x1) &&
@ -482,99 +440,71 @@ static void pctl_cfg(u32 channel,
break;
}
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[896],
(u32 *)&sdram_params->phy_regs.denali_phy[896],
(958 - 895) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[0],
(u32 *)&sdram_params->phy_regs.denali_phy[0],
(90 - 0 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[128],
(u32 *)&sdram_params->phy_regs.denali_phy[128],
(218 - 128 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[256],
(u32 *)&sdram_params->phy_regs.denali_phy[256],
(346 - 256 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[384],
(u32 *)&sdram_params->phy_regs.denali_phy[384],
(474 - 384 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[512],
(u32 *)&sdram_params->phy_regs.denali_phy[512],
(549 - 512 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[640],
(u32 *)&sdram_params->phy_regs.denali_phy[640],
(677 - 640 + 1) * 4);
copy_to_reg((u32 *)&ddr_publ_regs->denali_phy[768],
(u32 *)&sdram_params->phy_regs.denali_phy[768],
(805 - 768 + 1) * 4);
copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
set_ds_odt(channel, sdram_params);
/* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 */
/* dqs_tsel_wr_end[7:4] add Half cycle */
tmp = (read32(&ddr_publ_regs->denali_phy[84]) >> 8) & 0xff;
clrsetbits_le32((&ddr_publ_regs->denali_phy[84]),
0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&ddr_publ_regs->denali_phy[212]) >> 8) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[212],
0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&ddr_publ_regs->denali_phy[340]) >> 8) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[340],
0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&ddr_publ_regs->denali_phy[468]) >> 8) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[468],
0xff << 8, (tmp + 0x10) << 8);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
* dqs_tsel_wr_end[7:4] add Half cycle
*/
tmp = (read32(&denali_phy[84]) >> 8) & 0xff;
clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&denali_phy[212]) >> 8) & 0xff;
clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&denali_phy[340]) >> 8) & 0xff;
clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
tmp = (read32(&denali_phy[468]) >> 8) & 0xff;
clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
/*
* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
* dq_tsel_wr_end[7:4] add Half cycle
*/
tmp = (read32(&ddr_publ_regs->denali_phy[83]) >> 16) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[83],
0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&ddr_publ_regs->denali_phy[211]) >> 16) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[211],
0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&ddr_publ_regs->denali_phy[339]) >> 16) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[339],
0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&ddr_publ_regs->denali_phy[467]) >> 16) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[467],
0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&denali_phy[83]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&denali_phy[211]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&denali_phy[339]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
tmp = (read32(&denali_phy[467]) >> 16) & 0xff;
clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
phy_io_config(channel, sdram_params);
/* PHY_DLL_RST_EN */
clrsetbits_le32(&ddr_publ_regs->denali_phy[957],
0x3 << 24, 0x2 << 24);
clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
/*
* FIXME:
* need to care ERROR bit
*/
while (!(read32(&ddr_pctl_regs->denali_ctl[203]) & (1 << 3)))
while (!(read32(&denali_ctl[203]) & (1 << 3)))
;
clrsetbits_le32(&ddr_pctl_regs->denali_ctl[68],
PWRUP_SREFRESH_EXIT,
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
pwrup_srefresh_exit);
}
static void select_per_cs_training_index(u32 channel, u32 rank)
{
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
if ((read32(&ddr_publ_regs->denali_phy[84])>>16) & 1) {
if ((read32(&denali_phy[84])>>16) & 1) {
/*
* PHY_8/136/264/392
* phy_per_cs_training_index_X 1bit offset_24
*/
clrsetbits_le32(&ddr_publ_regs->denali_phy[8],
0x1 << 24, rank << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[136],
0x1 << 24, rank << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[264],
0x1 << 24, rank << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[392],
0x1 << 24, rank << 24);
clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
}
}
@ -590,31 +520,26 @@ static void check_write_leveling_value(u32 channel,
const struct rk3399_sdram_params
*sdram_params)
{
struct rk3399_ddr_pi_regs *ddr_pi_regs = rk3399_ddr_pi[channel];
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 wl_value[2][4];
u32 rank = sdram_params->ch[channel].rank;
for (i = 0; i < rank; i++) {
/* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[8], 0x1 << 24,
i << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[136], 0x1 << 24,
i << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[264], 0x1 << 24,
i << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[392], 0x1 << 24,
i << 24);
wl_value[i][0] = (read32(&ddr_publ_regs->denali_phy[63]) >>
16) & 0x3ff;
wl_value[i][1] = (read32(&ddr_publ_regs->denali_phy[191]) >>
16) & 0x3ff;
wl_value[i][2] = (read32(&ddr_publ_regs->denali_phy[319]) >>
16) & 0x3ff;
wl_value[i][3] = (read32(&ddr_publ_regs->denali_phy[447]) >>
16) & 0x3ff;
/*
* PHY_8/136/264/392
* phy_per_cs_training_index_X 1bit offset_24
*/
clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24);
clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24);
clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24);
clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24);
wl_value[i][0] = (read32(&denali_phy[63]) >> 16) & 0x3ff;
wl_value[i][1] = (read32(&denali_phy[191]) >> 16) & 0x3ff;
wl_value[i][2] = (read32(&denali_phy[319]) >> 16) & 0x3ff;
wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff;
}
for (i = 0; i < 4; i++) {
@ -622,20 +547,16 @@ static void check_write_leveling_value(u32 channel,
((wl_value[1][i] > 0x1E0) || (wl_value[1][i] < 0x20))) {
switch (i) {
case 0:
setbits_le32(&ddr_publ_regs->denali_phy[79],
0x1 << 16);
setbits_le32(&denali_phy[79], 0x1 << 16);
break;
case 1:
setbits_le32(&ddr_publ_regs->denali_phy[207],
0x1 << 16);
setbits_le32(&denali_phy[207], 0x1 << 16);
break;
case 2:
setbits_le32(&ddr_publ_regs->denali_phy[335],
0x1 << 16);
setbits_le32(&denali_phy[335], 0x1 << 16);
break;
case 3:
setbits_le32(&ddr_publ_regs->denali_phy[463],
0x1 << 16);
setbits_le32(&denali_phy[463], 0x1 << 16);
break;
default:
break;
@ -649,28 +570,25 @@ static void check_write_leveling_value(u32 channel,
udelay(100);
/* PI_60 PI_WRLVL_EN:RW:8:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[60],
0x3 << 8,
0x2 << 8);
clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[59],
(0x1 << 8) | (0x3 << 16),
clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16),
(0x1 << 8) | (i << 16));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:25 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
/*
* check status obs,
* if error maybe can not get leveling done
* PHY_40/168/296/424 phy_wrlvl_status_obs_X:0:13
*/
obs_0 = read32(&ddr_publ_regs->denali_phy[40]);
obs_1 = read32(&ddr_publ_regs->denali_phy[168]);
obs_2 = read32(&ddr_publ_regs->denali_phy[296]);
obs_3 = read32(&ddr_publ_regs->denali_phy[424]);
obs_0 = read32(&denali_phy[40]);
obs_1 = read32(&denali_phy[168]);
obs_2 = read32(&denali_phy[296]);
obs_3 = read32(&denali_phy[424]);
if (((obs_0 >> 12) & 0x1) ||
((obs_1 >> 12) & 0x1) ||
((obs_2 >> 12) & 0x1) ||
@ -687,7 +605,7 @@ static void check_write_leveling_value(u32 channel,
"check_write_leveling_value error!!!\n");
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
@ -695,21 +613,20 @@ static int data_training(u32 channel,
const struct rk3399_sdram_params *sdram_params,
u32 training_flag)
{
struct rk3399_ddr_pi_regs *ddr_pi_regs = rk3399_ddr_pi[channel];
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
setbits_le32(&ddr_publ_regs->denali_phy[927], (1 << 22));
setbits_le32(&denali_phy[927], (1 << 22));
if (training_flag == PI_FULL_TARINING) {
if (sdram_params->dramtype == LPDDR4) {
training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
PI_READ_LEVELING |
PI_WDQ_LEVELING;
PI_READ_LEVELING | PI_WDQ_LEVELING;
} else if (sdram_params->dramtype == LPDDR3) {
training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
PI_READ_GATE_TRAINING |
@ -725,25 +642,25 @@ static int data_training(u32 channel,
if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
for (i = 0; i < rank; i++) {
/* PI_100 PI_CALVL_EN:RW:8:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[100],
0x3 << 8,
0x2 << 8);
clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[92],
clrsetbits_le32(&denali_pi[92],
(0x1 << 16) | (0x3 << 24),
(0x1 << 16) | (i << 24));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
/*
* check status obs
* PHY_532/660/789 phy_adr_calvl_obs1_:0:32
*/
obs_0 = read32(&ddr_publ_regs->denali_phy[532]);
obs_1 = read32(&ddr_publ_regs->denali_phy[660]);
obs_2 = read32(&ddr_publ_regs->denali_phy[789]);
obs_0 = read32(&denali_phy[532]);
obs_1 = read32(&denali_phy[660]);
obs_2 = read32(&denali_phy[789]);
if (((obs_0 >> 30) & 0x3) ||
((obs_1 >> 30) & 0x3) ||
((obs_2 >> 30) & 0x3))
@ -758,7 +675,7 @@ static int data_training(u32 channel,
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
@ -766,28 +683,26 @@ static int data_training(u32 channel,
if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
for (i = 0; i < rank; i++) {
/* PI_60 PI_WRLVL_EN:RW:8:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[60],
0x3 << 8,
0x2 << 8);
clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[59],
clrsetbits_le32(&denali_pi[59],
(0x1 << 8) | (0x3 << 16),
(0x1 << 8) | (i << 16));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
/*
* check status obs, if error maybe can not
* get leveling done PHY_40/168/296/424
* phy_wrlvl_status_obs_X:0:13
*/
obs_0 = read32(&ddr_publ_regs->denali_phy[40]);
obs_1 = read32(&ddr_publ_regs->denali_phy[168]);
obs_2 = read32(&ddr_publ_regs->denali_phy[296]);
obs_3 = read32(&ddr_publ_regs->denali_phy[424]);
obs_0 = read32(&denali_phy[40]);
obs_1 = read32(&denali_phy[168]);
obs_2 = read32(&denali_phy[296]);
obs_3 = read32(&denali_phy[424]);
if (((obs_0 >> 12) & 0x1) ||
((obs_1 >> 12) & 0x1) ||
((obs_2 >> 12) & 0x1) ||
@ -806,7 +721,7 @@ static int data_training(u32 channel,
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
@ -814,30 +729,29 @@ static int data_training(u32 channel,
if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
for (i = 0; i < rank; i++) {
/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[80],
0x3 << 24,
0x2 << 24);
clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
/*
* PI_74 PI_RDLVL_GATE_REQ:WR:16:1
* PI_RDLVL_CS:RW:24:2
*/
clrsetbits_le32(&ddr_pi_regs->denali_pi[74],
clrsetbits_le32(&denali_pi[74],
(0x1 << 16) | (0x3 << 24),
(0x1 << 16) | (i << 24));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
/*
* check status obs
* PHY_43/171/299/427
* PHY_GTLVL_STATUS_OBS_x:16:8
*/
obs_0 = read32(&ddr_publ_regs->denali_phy[43]);
obs_1 = read32(&ddr_publ_regs->denali_phy[171]);
obs_2 = read32(&ddr_publ_regs->denali_phy[299]);
obs_3 = read32(&ddr_publ_regs->denali_phy[427]);
obs_0 = read32(&denali_phy[43]);
obs_1 = read32(&denali_phy[171]);
obs_2 = read32(&denali_phy[299]);
obs_3 = read32(&denali_phy[427]);
if (((obs_0 >> (16 + 6)) & 0x3) ||
((obs_1 >> (16 + 6)) & 0x3) ||
((obs_2 >> (16 + 6)) & 0x3) ||
@ -853,7 +767,7 @@ static int data_training(u32 channel,
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
@ -861,18 +775,17 @@ static int data_training(u32 channel,
if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
for (i = 0; i < rank; i++) {
/* PI_80 PI_RDLVL_EN:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[80],
0x3 << 16,
0x2 << 16);
clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[74],
clrsetbits_le32(&denali_pi[74],
(0x1 << 8) | (0x3 << 24),
(0x1 << 8) | (i << 24));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
/*
* make sure status obs not report error bit
* PHY_46/174/302/430
@ -886,7 +799,7 @@ static int data_training(u32 channel,
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
@ -897,20 +810,18 @@ static int data_training(u32 channel,
* disable PI_WDQLVL_VREF_EN before wdq leveling?
* PI_181 PI_WDQLVL_VREF_EN:RW:8:1
*/
clrbits_le32(&ddr_pi_regs->denali_pi[181], 0x1 << 8);
clrbits_le32(&denali_pi[181], 0x1 << 8);
/* PI_124 PI_WDQLVL_EN:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[124],
0x3 << 16,
0x2 << 16);
clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[121],
clrsetbits_le32(&denali_pi[121],
(0x1 << 8) | (0x3 << 16),
(0x1 << 8) | (i << 16));
select_per_cs_training_index(channel, i);
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
tmp = read32(&denali_pi[174]) >> 8;
if ((((tmp >> 12) & 0x1) == 0x1) &&
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 6) & 0x1) == 0x0))
@ -919,12 +830,12 @@ static int data_training(u32 channel,
return -1;
}
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&ddr_pi_regs->denali_pi[175]), 0x00003f7c);
write32((&denali_pi[175]), 0x00003f7c);
}
}
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
clrbits_le32(&ddr_publ_regs->denali_phy[927], (1 << 22));
clrbits_le32(&denali_phy[927], (1 << 22));
return 0;
}