pistachio: add SOC descriptor

With this descriptor added ramstage properly allocates memory
resources and creates entries in coreboot table. This also allows to
proceed to booting depthcharge, as it now can be loaded into the
existing memory.

BRANCH=none
BUG=chrome-os-partner:31438

TEST=with the set of patches applied the firmware properly finds
     depthcharge in CBFS, uncompresses it and attempts to start:

  ...
  Booting payload fallback/payload from cbfs
  Loading segment from rom address 0x9b000058
    code (compression=1)
    New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe
  Loading segment from rom address 0x9b000074
    Entry Point 0x80124038
  Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
  lb: [0x0000000080000000, 0x0000000080013858)
  Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
  using LZMA
  [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090
  Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054
  dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50
  Loaded segments
  BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129
  Jumping to boot code at 80124038
  ERROR: dropped a timestamp entry
  CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes
  entry    = 80124038

Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf
Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232571
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9192
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/google/urara/devicetree.cb

@@ -20,6 +20,7 @@
 #
 
 chip soc/imgtec/pistachio
+	device cpu_cluster 0 on end
 	chip drivers/generic/generic # I2C0 controller
 		device i2c 6 on end # Fake component for testing
 	end

src/soc/imgtec/pistachio/Makefile.inc

@@ -34,6 +34,7 @@ bootblock-y += monotonic_timer.c
 
 ramstage-y += cbmem.c
 ramstage-y += monotonic_timer.c
+ramstage-y += soc.c
 
 romstage-y += cbmem.c
 romstage-y += romstage.c

src/soc/imgtec/pistachio/soc.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 The Chromium OS Authors.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <symbols.h>
+
+static void soc_read_resources(device_t dev)
+{
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB,
+		     (CONFIG_DRAM_SIZE_MB * MiB) / KiB);
+}
+
+static void soc_init(device_t dev)
+{
+	printk(BIOS_INFO, "CPU: Imgtec Pistachio\n");
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.init		= soc_init,
+};
+
+static void enable_soc_dev(device_t dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_imgtec_pistachio_ops = {
+	CHIP_NAME("SOC: Imgtec Pistachio")
+	.enable_dev = enable_soc_dev,
+};