mb/google/kukui: Fix LCD sequence T3 fail issue
The T3 that PPVARN_LCD low to LCM_RST_1V8 high is 0.1269ms and it does not meet the LCD specification that the T3 must be larger than 5ms. Because there is a delay between PPVARN_LCD_EN and PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8 in order to meet the specification "ProductSpec_NV105WUM-A51_ V4.3_P2(TLCM).pdf". BUG=b:172201138 BRANCH=kukui TEST=The LCD sequence T3 is larger than 5ms when power on. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -91,7 +91,7 @@ static void power_on_panel(struct panel_description *panel)
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gpio_output(GPIO_PPVARN_LCD_EN, 1);
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gpio_output(GPIO_PPVARN_LCD_EN, 1);
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gpio_output(GPIO_PP1800_LCM_EN, 1);
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gpio_output(GPIO_PP1800_LCM_EN, 1);
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gpio_output(GPIO_PP3300_LCM_EN, 1);
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gpio_output(GPIO_PP3300_LCM_EN, 1);
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mdelay(6);
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mdelay(15);
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gpio_output(GPIO_LCM_RST_1V8, 1);
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gpio_output(GPIO_LCM_RST_1V8, 1);
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mdelay(6);
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mdelay(6);
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}
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}
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