mainboard/ocp/wedge100s: Initial commit
This patch does the following: 1. Copy src/mainboard/intel/camelbackmountain_fsp to src/mainboard/ocp/wedge100s. 2. Update Kconfig files 3. Add board.fmd 4. Enable VPD The OCP Wedge100S is a 100GbE top-of-rack switch with a Xeon D-1500 com-express module. More info is available at http://www.opencompute.org/wiki/Networking/SpecsAndDesigns. Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: Ia150b066124953c7c0abe8ea5a13e4131194ea00 Reviewed-on: https://review.coreboot.org/25671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
David Hendricks
David Hendricks
parent
99d3ef85cf
commit
f3e2205dfc
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@ -0,0 +1,50 @@
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if BOARD_OCP_WEDGE100S
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_FSP_BROADWELL_DE
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select TSC_MONOTONIC_TIMER
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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select SERIRQ_CONTINUOUS_MODE
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select SUPERIO_ITE_COMMON_ROMSTAGE
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select FSP_EHCI1_ENABLE
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config MAINBOARD_DIR
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string
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default "ocp/wedge100s"
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config MAINBOARD_PART_NUMBER
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string
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default "Wedge 100S"
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config IRQ_SLOT_COUNT
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int
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default 18
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config CBFS_SIZE
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hex
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default 0x00200000
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config VIRTUAL_ROM_SIZE
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hex
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default 0x1000000
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config DRIVERS_UART_8250IO
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def_bool n
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config FSP_PACKAGE_DEFAULT
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bool "Configure defaults for the Intel FSP package"
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default n
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
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endif # BOARD_OCP_WEDGE100S
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@ -0,0 +1,2 @@
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config BOARD_OCP_WEDGE100S
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bool "Wedge 100S"
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@ -0,0 +1,16 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-y += irqroute.c
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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@ -0,0 +1,56 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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Name(\APC1, Zero) // IIO IOAPIC
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Name(\PICM, Zero) // IOAPIC/8259
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Method(_PIC, 1)
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{
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Store(Arg0, PICM)
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}
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/ioapic.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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extern const unsigned char AmlCode[];
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unsigned long acpi_fill_madt(unsigned long current)
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{
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u32 i;
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current = acpi_create_madt_lapics(current);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8,
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IOXAPIC1_BASE_ADDRESS, 0);
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set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9,
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IOXAPIC2_BASE_ADDRESS, 24);
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set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9);
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current = acpi_madt_irq_overrides(current);
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for (i = 0; i < 16; i++)
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1);
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return current;
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}
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@ -0,0 +1,25 @@
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x800000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x7ff000
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}
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SI_BIOS@0x800000 0x800000 {
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FMAP@0x0 0x1000
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RW_MISC@0x1000 0xe000 {
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RW_ELOG@0x0 0x4000
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RW_VPD@0x4000 0x2000
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RW_MISC_UNUSED@0x6000 0x5000
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RW_NVRAM@0xc000 0x2000
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# UNIFIED_MRC_CACHE@0x10000 0x20000 {
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# RECOVERY_MRC_CACHE@0x0 0x10000
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# RW_MRC_CACHE@0x10000 0x10000
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# }
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}
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UNUSED@0xf000 0x1000 {
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# This only exists to satisfy tools that
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# specifically look for RO_VPD.
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RO_VPD@0x0 0x1000
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}
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COREBOOT(CBFS)@0x10000 0x7f0000
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}
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}
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@ -0,0 +1,5 @@
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Board name: Wedge 100S
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Category: server
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ROM protocol: SPI
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ROM socketed: yes
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Release year: 2017
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@ -0,0 +1,119 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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#411 5 r 0 unused
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# MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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||||
6 1 Alert
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6 2 Critical
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6 3 Error
|
||||
6 4 Warning
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||||
6 5 Notice
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||||
6 6 Info
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||||
6 7 Debug
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||||
6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,15 @@
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chip soc/intel/fsp_broadwell_de
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
|
||||
device pci 00.0 on end # SoC router
|
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device pci 14.0 on end # xHCI Controller
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device pci 19.0 on end # Gigabit LAN Controller
|
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device pci 1d.0 on end # EHCI Controller
|
||||
device pci 1f.0 on end # LPC Bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
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device pci 1f.3 on end # SMBus Controller
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device pci 1f.5 on end # SATA Controller
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end
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end
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@ -0,0 +1,293 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 Google Inc.
|
||||
* Copyright (C) 2015-2016 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <acpi/southcluster.asl>
|
||||
#include <acpi/pcie1.asl>
|
||||
}
|
||||
|
||||
Name (PRUN, Package() {
|
||||
Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
|
||||
Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
|
||||
Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
|
||||
Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
|
||||
Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
|
||||
})
|
||||
|
||||
Name (ARUN, Package() {
|
||||
Package() { 0x0008FFFF, 0, 0, 16 },
|
||||
Package() { 0x0008FFFF, 1, 0, 17 },
|
||||
Package() { 0x0008FFFF, 2, 0, 18 },
|
||||
Package() { 0x0008FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0009FFFF, 0, 0, 16 },
|
||||
Package() { 0x0009FFFF, 1, 0, 17 },
|
||||
Package() { 0x0009FFFF, 2, 0, 18 },
|
||||
Package() { 0x0009FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000AFFFF, 0, 0, 16 },
|
||||
Package() { 0x000AFFFF, 1, 0, 17 },
|
||||
Package() { 0x000AFFFF, 2, 0, 18 },
|
||||
Package() { 0x000AFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000BFFFF, 0, 0, 16 },
|
||||
Package() { 0x000BFFFF, 1, 0, 17 },
|
||||
Package() { 0x000BFFFF, 2, 0, 18 },
|
||||
Package() { 0x000BFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000CFFFF, 0, 0, 16 },
|
||||
Package() { 0x000CFFFF, 1, 0, 17 },
|
||||
Package() { 0x000CFFFF, 2, 0, 18 },
|
||||
Package() { 0x000CFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000DFFFF, 0, 0, 16 },
|
||||
Package() { 0x000DFFFF, 1, 0, 17 },
|
||||
Package() { 0x000DFFFF, 2, 0, 18 },
|
||||
Package() { 0x000DFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000EFFFF, 0, 0, 16 },
|
||||
Package() { 0x000EFFFF, 1, 0, 17 },
|
||||
Package() { 0x000EFFFF, 2, 0, 18 },
|
||||
Package() { 0x000EFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x000FFFFF, 0, 0, 16 },
|
||||
Package() { 0x000FFFFF, 1, 0, 17 },
|
||||
Package() { 0x000FFFFF, 2, 0, 18 },
|
||||
Package() { 0x000FFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0010FFFF, 0, 0, 16 },
|
||||
Package() { 0x0010FFFF, 1, 0, 17 },
|
||||
Package() { 0x0010FFFF, 2, 0, 18 },
|
||||
Package() { 0x0010FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0011FFFF, 0, 0, 16 },
|
||||
Package() { 0x0011FFFF, 1, 0, 17 },
|
||||
Package() { 0x0011FFFF, 2, 0, 18 },
|
||||
Package() { 0x0011FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0012FFFF, 0, 0, 16 },
|
||||
Package() { 0x0012FFFF, 1, 0, 17 },
|
||||
Package() { 0x0012FFFF, 2, 0, 18 },
|
||||
Package() { 0x0012FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0013FFFF, 0, 0, 16 },
|
||||
Package() { 0x0013FFFF, 1, 0, 17 },
|
||||
Package() { 0x0013FFFF, 2, 0, 18 },
|
||||
Package() { 0x0013FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0014FFFF, 0, 0, 16 },
|
||||
Package() { 0x0014FFFF, 1, 0, 17 },
|
||||
Package() { 0x0014FFFF, 2, 0, 18 },
|
||||
Package() { 0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0016FFFF, 0, 0, 16 },
|
||||
Package() { 0x0016FFFF, 1, 0, 17 },
|
||||
Package() { 0x0016FFFF, 2, 0, 18 },
|
||||
Package() { 0x0016FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0017FFFF, 0, 0, 16 },
|
||||
Package() { 0x0017FFFF, 1, 0, 17 },
|
||||
Package() { 0x0017FFFF, 2, 0, 18 },
|
||||
Package() { 0x0017FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0018FFFF, 0, 0, 16 },
|
||||
Package() { 0x0018FFFF, 1, 0, 17 },
|
||||
Package() { 0x0018FFFF, 2, 0, 18 },
|
||||
Package() { 0x0018FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x0019FFFF, 0, 0, 16 },
|
||||
Package() { 0x0019FFFF, 1, 0, 17 },
|
||||
Package() { 0x0019FFFF, 2, 0, 18 },
|
||||
Package() { 0x0019FFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x001CFFFF, 0, 0, 16 },
|
||||
Package() { 0x001CFFFF, 1, 0, 17 },
|
||||
Package() { 0x001CFFFF, 2, 0, 18 },
|
||||
Package() { 0x001CFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x001DFFFF, 0, 0, 16 },
|
||||
Package() { 0x001DFFFF, 1, 0, 17 },
|
||||
Package() { 0x001DFFFF, 2, 0, 18 },
|
||||
Package() { 0x001DFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x001EFFFF, 0, 0, 16 },
|
||||
Package() { 0x001EFFFF, 1, 0, 17 },
|
||||
Package() { 0x001EFFFF, 2, 0, 18 },
|
||||
Package() { 0x001EFFFF, 3, 0, 19 },
|
||||
|
||||
Package() { 0x001FFFFF, 0, 0, 16 },
|
||||
Package() { 0x001FFFFF, 1, 0, 17 },
|
||||
Package() { 0x001FFFFF, 2, 0, 18 },
|
||||
Package() { 0x001FFFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Device (UNC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_UID, 0x3F)
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (0xff)
|
||||
}
|
||||
|
||||
Name (_ADR, 0x00)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xf)
|
||||
}
|
||||
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
0x0000, // Granularity
|
||||
0x00FF, // Range Minimum
|
||||
0x00FF, // Range Maximum
|
||||
0x0000, // Translation Offset
|
||||
0x0001, // Length
|
||||
,, )
|
||||
})
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (PICM, Zero))
|
||||
{
|
||||
Return (PRUN)
|
||||
}
|
||||
|
||||
Return (ARUN)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
acpi_fill_in_fadt(fadt, facs, dsdt);
|
||||
|
||||
/* Platform specific customizations go here */
|
||||
|
||||
header->checksum = 0;
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "irqroute.h"
|
||||
|
||||
DEFINE_IRQ_ROUTES;
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2015-2016 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef IRQROUTE_H
|
||||
#define IRQROUTE_H
|
||||
|
||||
#include <soc/irq.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
||||
#define PCI_DEV_PIRQ_ROUTES \
|
||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D)
|
||||
|
||||
/*
|
||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
||||
* Reserved: 0, 1, 2, 8, 13
|
||||
* ACPI/SCI: 9
|
||||
*/
|
||||
#define PIRQ_PIC_ROUTES \
|
||||
PIRQ_PIC(A, 5), \
|
||||
PIRQ_PIC(B, 6), \
|
||||
PIRQ_PIC(C, 7), \
|
||||
PIRQ_PIC(D, 10), \
|
||||
PIRQ_PIC(E, 11), \
|
||||
PIRQ_PIC(F, 12), \
|
||||
PIRQ_PIC(G, 14), \
|
||||
PIRQ_PIC(H, 15)
|
||||
|
||||
#endif /* IRQROUTE_H */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <device/device.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
|
||||
#include <x86emu/x86emu.h>
|
||||
#endif
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/interrupt.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
/*
|
||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
||||
* This is the earliest point to add customization.
|
||||
*/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done before fsp init
|
||||
*
|
||||
*/
|
||||
void early_mainboard_romstage_entry(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done after fsp init
|
||||
*
|
||||
*/
|
||||
void late_mainboard_romstage_entry(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief customize fsp parameters here if needed
|
||||
*/
|
||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
||||
{
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue