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mb/google/sarien: Update GPIO GPP_C23 setting 

GPIO pin GPP_C23 is used as level trigger but not edge trigger, also it
is not inverted, correct it here. According to board schematic, GPP_C23
connected with 3.3v pull up, so the pin is low active.

BUG=b:128554235
TEST=Boot up arcada platform with stylus keep on touching the screen,
the touch screen is still functional once in OS stage. Without change,
touch screen is not functional at same scenario.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I2bee664198057e3997dda181a16b9a0388067036
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32347
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2019-04-17 11:21:17 -07:00 committed by Duncan Laurie
parent b34de93153
commit f3ea181d98
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/sarien/variants/arcada/gpio.c
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@ -104,7 +104,7 @@ static const struct pad_config gpio_table[] = {
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TS_INT# */ LEVEL, NONE), /* TS_INT# */
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */