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baytrail: correct MMC pci location 

The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.

MMC is at 00:17.0 with a device id of 0x0f50.

BUG=None
BRANCH=None
TEST=Built.

Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4884
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2013-10-11 08:39:54 -05:00 committed by Aaron Durbin
parent 9d9d7f0429
commit f3f409bf55
1 changed files with 5 additions and 5 deletions
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10
src/soc/intel/baytrail/baytrail/pci_devs.h
View File

@ -32,11 +32,6 @@
#define GFX_FUNC 0
# define GFX_DEVID 0x0f31
/* MMC Port */
#define MMC_DEV 16
#define MMC_FUNC 0
# define MMC_DEVID 0x0f14
/* SDIO Port */
#define SDIO_DEV 17
#define SDIO_FUNC 0
@ -63,6 +58,11 @@
#define LPE_FUNC 0
# define LPE_DEVID 0x0f28
/* MMC Port */
#define MMC_DEV 23
#define MMC_FUNC 0
# define MMC_DEVID 0x0f50
/* Serial IO 1 */
#define SIO1_DEV 24
# define SIO_DMA1_DEV SIO1_DEV