soc/intel/tigerlake: Add USBOTG and CrashLog to irq table

FSP reports missing IRQ for devices.

Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain.

Bug = N/A
TEST = Build and boot Siemens AS-TGL1

Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/tigerlake/fsp_params.c

@@ -145,6 +145,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 	{
 		.slot = PCH_DEV_SLOT_SIO0,
 		.fns = {
+			ANY_PIRQ(PCH_DEVFN_CT),
 			ANY_PIRQ(PCH_DEVFN_THC0),
 			ANY_PIRQ(PCH_DEVFN_THC1),
 		},
@@ -172,6 +173,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
 		.slot = PCH_DEV_SLOT_XHCI,
 		.fns = {
 			ANY_PIRQ(PCH_DEVFN_XHCI),
+			DIRECT_IRQ(PCH_DEVFN_USBOTG),
 			FIXED_INT_ANY_PIRQ(PCH_DEVFN_CNVI_WIFI, PCI_INT_A),
 		},
 	},

src/soc/intel/tigerlake/include/soc/pci_devs.h

@@ -80,6 +80,7 @@
 /* PCH Devices */
 #define MIN_PCH_SLOT		PCH_DEV_SLOT_SIO0
 #define PCH_DEV_SLOT_SIO0	0x10
+#define  PCH_DEVFN_CT		_PCH_DEVFN(SIO0, 0)
 #define  PCH_DEVFN_THC0		_PCH_DEVFN(SIO0, 6)
 #define  PCH_DEVFN_THC1		_PCH_DEVFN(SIO0, 7)
 #define  PCH_DEV_THC0		_PCH_DEV(SIO0, 6)