diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
index 65202cb6d4..81ead2e554 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
@@ -65,9 +65,9 @@ Device (CRHW)
 	Method(GPIO, 0, Serialized)
 	{
 		Name(OIPG, Package() {
-			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
-			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
-			Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
+			Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
+			Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
 			Package() { 0x100, 0,  9, "CougarPoint" }, // debug header gpio
 			Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1
 			Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 0acd20f44b..850af7b32b 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -45,36 +45,30 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	if (!gpio_base)
 		return;
 
-#if 0 // Dev mode is hardcoded on, so we don't need to read these GPIOs.
 	u32 gp_lvl = inl(gpio_base + 0x0c);
-#endif
 	u32 gp_lvl2 = inl(gpio_base + 0x38);
-	u32 gp_lvl3 = inl(gpio_base + 0x48);
+	/* u32 gp_lvl3 = inl(gpio_base + 0x48); */
 
 	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
 	gpios->count = GPIO_COUNT;
 
-	/* Write Protect: GPIO68 = CHP3_SPI_WP */
-	gpios->gpios[0].port = 68;
-	gpios->gpios[0].polarity = ACTIVE_HIGH;
-	gpios->gpios[0].value = (gp_lvl3 >> (68-64)) & 1;
+	/* Write Protect: GPIO48 */
+	gpios->gpios[0].port = 48;
+	gpios->gpios[0].polarity = ACTIVE_LOW;
+	gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1;
 	strncpy((char *)gpios->gpios[0].name,"write protect",
 							GPIO_MAX_NAME_LENGTH);
 
-	/* Recovery: GPIO42 = CHP3_REC_MODE# */
-	gpios->gpios[1].port = 42;
+	/* Recovery: GPIO22 */
+	gpios->gpios[1].port = 22;
 	gpios->gpios[1].polarity = ACTIVE_LOW;
-	gpios->gpios[1].value = (gp_lvl2 >> (42-32)) & 1;
+	gpios->gpios[1].value = (gp_lvl >> 22) & 1;
 	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
 
-	/* Developer: GPIO17 = KBC3_DVP_MODE */
-	gpios->gpios[2].port = 17;
+	/* Developer: GPIO57 */
+	gpios->gpios[2].port = 57;
 	gpios->gpios[2].polarity = ACTIVE_HIGH;
-#if 0 // Dev mode is hardcoded on.
-	gpios->gpios[2].value = (gp_lvl >> 17) & 1;
-#else
-	gpios->gpios[2].value = 1;
-#endif
+	gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1;
 	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
 
 	/* Hard code the lid switch GPIO to open. */
@@ -93,7 +87,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 int get_developer_mode_switch(void)
 {
-#if 0 // Dev mode is hardcoded on.
 	device_t dev;
 #ifdef __PRE_RAM__
 	dev = PCI_DEV(0, 0x1f, 0);
@@ -101,13 +94,10 @@ int get_developer_mode_switch(void)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 #endif
 	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-	u32 gp_lvl = inl(gpio_base + 0x0c);
+	u32 gp_lvl2 = inl(gpio_base + 0x38);
 
-	/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
-	return (gp_lvl >> 17) & 1;
-#else
-	return 1;
-#endif
+	/* Developer: GPIO17, active high */
+	return (gp_lvl2 >> (57-32)) & 1;
 }
 
 int get_recovery_mode_switch(void)
@@ -119,9 +109,9 @@ int get_recovery_mode_switch(void)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 #endif
 	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-	u32 gp_lvl2 = inl(gpio_base + 0x38);
+	u32 gp_lvl = inl(gpio_base + 0x0c);
 
-	/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
-	return !((gp_lvl2 >> (42-32)) & 1);
+	/* Recovery: GPIO22, active low */
+	return !((gp_lvl >> 22) & 1);
 }
 
diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h
index bec34aacb3..c458c839ab 100644
--- a/src/mainboard/intel/emeraldlake2/gpio.h
+++ b/src/mainboard/intel/emeraldlake2/gpio.h
@@ -34,6 +34,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = {
         .gpio12 = GPIO_MODE_GPIO,
         .gpio15 = GPIO_MODE_GPIO,
         .gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
         .gpio24 = GPIO_MODE_GPIO,
         .gpio27 = GPIO_MODE_GPIO,
         .gpio28 = GPIO_MODE_GPIO,
@@ -49,6 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = {
         .gpio12 = GPIO_DIR_INPUT,
         .gpio15 = GPIO_DIR_INPUT,
         .gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
         .gpio27 = GPIO_DIR_INPUT,
 };
 
@@ -60,11 +62,13 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = {
 
 const struct pch_gpio_set2 pch_gpio_set2_mode = {
         .gpio36 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
         .gpio57 = GPIO_MODE_GPIO,
         .gpio60 = GPIO_MODE_GPIO,
 };
 
 const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio48 = GPIO_DIR_INPUT,
         .gpio57 = GPIO_DIR_INPUT,
 };