mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into references
Change-Id: I58e5dfa57856e80d1a5e4a6fab0b2523301fa8f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80048 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
This commit is contained in:
parent
c01ce0f88d
commit
f40e59c838
10 changed files with 119 additions and 119 deletions
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x1815 inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 off end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -24,17 +24,17 @@ chip northbridge/intel/sandybridge
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine KT
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3, SD/MMC
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device pci 1c.3 on end # PCIe Port #4, WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref xhci on end # USB 3.0 Controller
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device ref mei1 on end # Management Engine KT
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 off end # PCIe Port #2
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
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device ref pcie_rp4 on end # PCIe Port #4, WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x162b inherit
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device pci 01.0 off end # PEG
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device pci 02.0 on end # iGPU
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device ref peg10 off end # PEG
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device ref igd on end # iGPU
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -21,24 +21,24 @@ chip northbridge/intel/sandybridge
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# HDD(0), ODD(1), eSATA(4), dock eSATA(5)
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register "sata_port_map" = "0x33"
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.1 on # PCIe Port #2, ExpressCard
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device ref pcie_rp1 off end # PCIe Port #1
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device ref pcie_rp2 on # PCIe Port #2, ExpressCard
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smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
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"ExpressCard Slot" "SlotDataBusWidth1X"
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end
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device pci 1c.2 on end # PCIe Port #3, SD/MMC Host Controller
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device pci 1c.3 on # PCIe Port #4, WLAN
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC Host Controller
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device ref pcie_rp4 on # PCIe Port #4, WLAN
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smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
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"SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
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end
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on # PCIe Port #7, WWAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 on # PCIe Port #7, WWAN
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smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
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"SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X"
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end
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x60"
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register "ec_cmd_port" = "0x64"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x17df inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 off end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -23,16 +23,16 @@ chip northbridge/intel/sandybridge
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2, ExpressCard
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device pci 1c.2 on end # PCIe Port #3, SD/MMC
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device pci 1c.3 on end # PCIe Port #4, WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref xhci on end # USB 3.0 Controller
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
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device ref pcie_rp4 on end # PCIe Port #4, WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x162a inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 off end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -20,15 +20,15 @@ chip northbridge/intel/sandybridge
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "sata_port_map" = "0x21"
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2, ExpressCard
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device pci 1c.2 on end # PCIe Port #3, SD/MMC
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device pci 1c.3 on end # WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7, WWAN
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
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device ref pcie_rp4 on end # WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 on end # PCIe Port #7, WWAN
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x60"
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register "ec_cmd_port" = "0x64"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x161c inherit
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 on end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -21,16 +21,16 @@ chip northbridge/intel/sandybridge
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# HDD(0), ODD(1), docking(3,5), eSATA(4)
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register "sata_port_map" = "0x3b"
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device pci 16.3 on end # Management Engine KT
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2, ExpressCard
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device pci 1c.2 on end # PCIe Port #3, SD/MMC
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device pci 1c.3 on end # PCIe Port #4, WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7, WWAN
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device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller
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device pci 1f.0 on # LPC bridge
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device ref me_kt on end # Management Engine KT
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
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device ref pcie_rp4 on end # PCIe Port #4, WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 on end # PCIe Port #7, WWAN
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device ref pcie_rp8 on end # PCIe Port #8, NEC USB 3.0 Host Controller
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x60"
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register "ec_cmd_port" = "0x64"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x179b inherit
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 on end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -24,17 +24,17 @@ chip northbridge/intel/sandybridge
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.3 on end # Management Engine KT
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2, ExpressCard
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device pci 1c.2 on end # PCIe Port #3, SD/MMC
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device pci 1c.3 on end # PCIe Port #4, WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref xhci on end # USB 3.0 Controller
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device ref me_kt on end # Management Engine KT
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
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device ref pcie_rp4 on end # PCIe Port #4, WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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@ -5,11 +5,11 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x176c inherit
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device pci 01.0 on # PCIe Bridge for discrete graphics
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device ref peg10 on # PCIe Bridge for discrete graphics
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device pci 00.0 on end # GPU
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device pci 00.1 on end # HDMI Audio on GPU
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end
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device pci 02.0 off end # Internal graphics
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device ref igd off end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
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register "docking_supported" = "0"
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@ -25,16 +25,16 @@ chip northbridge/intel/sandybridge
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 on end # Media Card and FireWire host controller
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device pci 1c.3 on end # Wireless LAN Adapter
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device pci 1c.4 on end # SATA Controller 2 for dock
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref xhci on end # USB 3.0 Controller
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2
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device ref pcie_rp3 on end # Media Card and FireWire host controller
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device ref pcie_rp4 on end # Wireless LAN Adapter
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device ref pcie_rp5 on end # SATA Controller 2 for dock
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x18df inherit
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # Internal graphics
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device ref peg10 off end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# mailbox at 0x200/0x201 and PM1 at 0x220
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@ -23,16 +23,16 @@ chip northbridge/intel/sandybridge
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3 SDHCI
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device pci 1c.3 on end # PCIe Port #4 WLAN
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on # LPC bridge
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device ref xhci on end # USB 3.0 Controller
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 off end # PCIe Port #2
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device ref pcie_rp3 on end # PCIe Port #3 SDHCI
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device ref pcie_rp4 on end # PCIe Port #4 WLAN
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref lpc on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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@ -6,8 +6,8 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x1621 inherit
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device pci 01.0 off end # PEG
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device pci 02.0 on end # iGPU
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device ref peg10 off end # PEG
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device ref igd on end # iGPU
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "gen1_dec" = "0x007c0201"
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# FIXME: ports 3, 5 are untested
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register "sata_port_map" = "0x3b"
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on # PCIe Port #2, ExpressCard
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 on # PCIe Port #2, ExpressCard
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smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
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"ExpressCard Slot" "SlotDataBusWidth1X"
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end
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device pci 1c.2 on end # PCIe Port #3, SD/MMC and FireWire
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device pci 1c.3 on # PCIe Port #4, WLAN
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device ref pcie_rp3 on end # PCIe Port #3, SD/MMC and FireWire
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device ref pcie_rp4 on # PCIe Port #4, WLAN
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smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
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"SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
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end
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7, WWAN
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device pci 1c.7 off end # PCIe Port #8
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device pci 1f.0 on
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device ref pcie_rp5 off end # PCIe Port #5
|
||||
device ref pcie_rp6 off end # PCIe Port #6
|
||||
device ref pcie_rp7 on end # PCIe Port #7, WWAN
|
||||
device ref pcie_rp8 off end # PCIe Port #8
|
||||
device ref lpc on
|
||||
chip ec/hp/kbc1126
|
||||
register "ec_data_port" = "0x60"
|
||||
register "ec_cmd_port" = "0x64"
|
||||
|
|
|
@ -7,8 +7,8 @@ chip northbridge/intel/sandybridge
|
|||
device domain 0 on
|
||||
subsystemid 0x103c 0x18f8 inherit
|
||||
|
||||
device pci 01.0 off end # PCIe Bridge for discrete graphics
|
||||
device pci 02.0 on end # Internal graphics
|
||||
device ref peg10 off end # PCIe Bridge for discrete graphics
|
||||
device ref igd on end # Internal graphics
|
||||
|
||||
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
# mailbox at 0x200/0x201 and PM1 at 0x220
|
||||
|
@ -23,16 +23,16 @@ chip northbridge/intel/sandybridge
|
|||
register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
register "xhci_switchable_ports" = "0x0000000f"
|
||||
|
||||
device pci 14.0 on end # USB 3.0 Controller
|
||||
device pci 1c.0 on end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 on end # PCIe Port #3
|
||||
device pci 1c.3 on end # PCIe Port #4
|
||||
device pci 1c.4 off end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1c.6 off end # PCIe Port #7
|
||||
device pci 1c.7 off end # PCIe Port #8
|
||||
device pci 1f.0 on # LPC bridge
|
||||
device ref xhci on end # USB 3.0 Controller
|
||||
device ref pcie_rp1 on end # PCIe Port #1
|
||||
device ref pcie_rp2 off end # PCIe Port #2
|
||||
device ref pcie_rp3 on end # PCIe Port #3
|
||||
device ref pcie_rp4 on end # PCIe Port #4
|
||||
device ref pcie_rp5 off end # PCIe Port #5
|
||||
device ref pcie_rp6 off end # PCIe Port #6
|
||||
device ref pcie_rp7 off end # PCIe Port #7
|
||||
device ref pcie_rp8 off end # PCIe Port #8
|
||||
device ref lpc on # LPC bridge
|
||||
chip ec/hp/kbc1126
|
||||
register "ec_data_port" = "0x62"
|
||||
register "ec_cmd_port" = "0x66"
|
||||
|
|
Loading…
Reference in a new issue