GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/amd/*/hudson: Use CF9 reset 

Implement board_reset() as "system reset".

Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29057
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2018-10-07 13:25:59 +02:00 committed by Patrick Georgi
parent 3e1b3b1f4f
commit f4181052af
4 changed files with 22 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/southbridge/amd/agesa/hudson/Kconfig
View File

@ -15,24 +15,22 @@
config SOUTHBRIDGE_AMD_AGESA_BOLTON
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config SOUTHBRIDGE_AMD_AGESA_HUDSON
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config SOUTHBRIDGE_AMD_AGESA_YANGTZE
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_CF9_RESET
select HAVE_CF9_RESET_PREPARE
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/agesa/hudson/bootblock.c"

11
src/southbridge/amd/agesa/hudson/reset.c
View File

@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cf9_reset.h>
#include <reset.h>
#define HT_INIT_CONTROL 0x6c
@ -24,7 +25,7 @@
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
static void set_bios_reset(void)
void cf9_reset_prepare(void)
{
u32 htic;
htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
@ -32,11 +33,7 @@ static void set_bios_reset(void)
pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
void do_hard_reset(void)
void do_board_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
system_reset();
}

16
src/southbridge/amd/pi/hudson/Kconfig
View File

@ -15,27 +15,25 @@
config SOUTHBRIDGE_AMD_PI_BOLTON
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config SOUTHBRIDGE_AMD_PI_AVALON
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config SOUTHBRIDGE_AMD_PI_KERN
bool
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
config HUDSON_DISABLE_IMC
bool
if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_CF9_RESET
select HAVE_CF9_RESET_PREPARE
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/pi/hudson/bootblock.c"

12
src/southbridge/amd/pi/hudson/reset.c
View File

@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cf9_reset.h>
#include <reset.h>
#define HT_INIT_CONTROL 0x6c
@ -24,7 +25,7 @@
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
static void set_bios_reset(void)
void cf9_reset_prepare(void)
{
u32 htic;
htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
@ -32,12 +33,7 @@ static void set_bios_reset(void)
pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
void do_hard_reset(void)
void do_board_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
system_reset();
}