intel/fsp_baytrail: Load BSP microcode in bootblock
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
3ecfdbde14
commit
f41ad02c83
|
@ -18,6 +18,7 @@
|
|||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/intel/microcode/microcode.c>
|
||||
#include <baytrail/iosf.h>
|
||||
#include <baytrail/pci_devs.h>
|
||||
#include <baytrail/spi.h>
|
||||
|
@ -112,9 +113,11 @@ static void set_up_lpc_pads(void)
|
|||
|
||||
static void bootblock_cpu_init(void)
|
||||
{
|
||||
|
||||
check_for_warm_reset();
|
||||
|
||||
/* Load microcode before any caching. */
|
||||
intel_update_microcode_from_cbfs();
|
||||
|
||||
/* Allow memory-mapped PCI config access. */
|
||||
setup_mmconfig();
|
||||
enable_rom_caching();
|
||||
|
|
Loading…
Reference in New Issue