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mediatek: Refine whitespace and formating changes 

This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.

BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
     of the patches applied) and Elm platform

Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Tristan Shieh 2018-06-06 12:52:20 +08:00 committed by Patrick Georgi
parent 794284ff0e
commit f42db110d0
17 changed files with 59 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@ -264,7 +264,7 @@ static void mem_pll_phase_cali(u32 channel)
}
}
udelay(20); /* delay 20us for external loop pll stable */
udelay(20); /* delay 20us for external loop pll stable */
/* 2. enable mempll 2 3 4 jitter meter */
for (i = 0; i < 3; i++)
@ -323,7 +323,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
for (channel = 0; channel < CHANNEL_NUM; channel++)
mem_pll_init_set_params(channel);
udelay(1); /* wait after da_mpll_sdm_iso_en goes low */
udelay(1); /* wait after da_mpll_sdm_iso_en goes low */
/* only set once in MPLL */
mt_mem_pll_config_post();
@ -391,7 +391,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
/* unrequest mempll reset/pdn mode and wait settle */
clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);
udelay(31); /* PLL ready */
udelay(31); /* PLL ready */
for (channel = 0; channel < CHANNEL_NUM; channel++)
mem_pll_init_phase_sync(channel);
@ -402,7 +402,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
for (channel = 0; channel < CHANNEL_NUM; channel++)
mem_pll_phase_cali(channel);
div2_phase_sync(); /* phase sync for channel B */
div2_phase_sync(); /* phase sync for channel B */
mt_mem_pll_mux();
}
@ -584,7 +584,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params)
write32(&ch[channel].ao_regs->padctl4, 0x1 << 2 |
0x1 << 0);
udelay(200); /* tINIT3 > 200us */
udelay(200); /* tINIT3 > 200us */
write32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 24 |
0x1 << 20);
@ -682,7 +682,7 @@ void dramc_phy_reset(u32 channel)
setbits_le32(&ch[channel].ao_regs->gddr3ctl1,
1 << GDDR3CTL1_RDATRST_SHIFT);
udelay(1); /* delay 1ns */
udelay(1); /* delay 1ns */
clrbits_le32(&ch[channel].ao_regs->gddr3ctl1,
1 << GDDR3CTL1_RDATRST_SHIFT);

8
src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
View File

@ -37,7 +37,7 @@ void sw_impedance_cal(u32 channel,
dramc_dbg_msg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp);
dramc_dbg_msg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn);
mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */
mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */
value = params->impedance_drvp << 28 | params->impedance_drvn << 24 |
params->impedance_drvp << 12 | params->impedance_drvn << 8;
@ -101,7 +101,7 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params)
/* CKE and CS delay */
ca_shift_avg32 = (u32)(ca_shift_avg8 + (CATRAINING_NUM >> 1));
ca_shift_avg32 /= (u32) CATRAINING_NUM;
ca_shift_avg32 /= (u32)CATRAINING_NUM;
/* CKEDLY */
clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[4],
@ -201,7 +201,7 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val)
coarse_tune_start = 15;
}
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
/* Rank 0 P0/P1 coarse tune settings */
clrsetbits_le32(&ch[channel].ao_regs->dqsctl1,
@ -248,7 +248,7 @@ static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl)
{
u8 curr_val_p1, r1dqsgate, r1dqsgate_p1;
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
clrsetbits_le32(&ch[channel].ao_regs->dqsctl2,
0xf << DQSCTL2_DQSINCTL_SHIFT,

27
src/soc/mediatek/mt8173/include/soc/ddp.h
View File

@ -142,7 +142,7 @@ struct mmsys_cfg_regs {
check_member(mmsys_cfg_regs, mmsys_sw1_rst_b, 0x144);
check_member(mmsys_cfg_regs, hdmi_en, 0x904);
static struct mmsys_cfg_regs * const mmsys_cfg = (void *) MMSYS_BASE;
static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE;
/* DISP_REG_CONFIG_MMSYS_CG_CON0
Configures free-run clock gating 0
@ -240,7 +240,7 @@ struct disp_mutex_regs {
};
check_member(disp_mutex_regs, debug_out_sel, 0x100);
static struct disp_mutex_regs * const disp_mutex = (void *) DISP_MUTEX_BASE;
static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
enum {
MUTEX_MOD_DISP_OVL0 = BIT(11),
@ -306,8 +306,9 @@ struct disp_ovl_regs {
};
check_member(disp_ovl_regs, l3_addr, 0xFA0);
static struct disp_ovl_regs * const disp_ovl[2] =
{(void *) DIS_OVL0_BASE, (void *) DIS_OVL1_BASE};
static struct disp_ovl_regs *const disp_ovl[2] = {
(void *)DIS_OVL0_BASE, (void *)DIS_OVL1_BASE
};
struct disp_rdma_regs {
u32 int_enable;
@ -341,8 +342,11 @@ enum {
};
check_member(disp_rdma_regs, debug_out_sel, 0x94);
static struct disp_rdma_regs * const disp_rdma[3] =
{(void *)DISP_RDMA0_BASE, (void *)DISP_RDMA1_BASE, (void *)DISP_RDMA2_BASE};
static struct disp_rdma_regs *const disp_rdma[3] = {
(void *)DISP_RDMA0_BASE,
(void *)DISP_RDMA1_BASE,
(void *)DISP_RDMA2_BASE
};
struct disp_od_regs {
u32 en;
@ -363,7 +367,7 @@ struct disp_od_regs {
};
check_member(disp_od_regs, misc, 0x48);
static struct disp_od_regs * const disp_od = (void *)DISP_OD_BASE;
static struct disp_od_regs *const disp_od = (void *)DISP_OD_BASE;
enum {
OD_RELAY_MODE = BIT(0),
@ -396,7 +400,7 @@ struct disp_ufoe_regs {
};
check_member(disp_ufoe_regs, dbg[7], 0x15C);
static struct disp_ufoe_regs * const disp_ufoe = (void *)DISP_UFOE_BASE;
static struct disp_ufoe_regs *const disp_ufoe = (void *)DISP_UFOE_BASE;
enum {
UFO_BYPASS = BIT(2),
@ -407,7 +411,7 @@ struct disp_split_regs {
u32 start;
};
static struct disp_split_regs * const disp_split = (void *)DISP_SPLIT1_BASE;
static struct disp_split_regs *const disp_split = (void *)DISP_SPLIT1_BASE;
struct disp_color_regs {
u8 reserved0[1024];
@ -423,8 +427,9 @@ check_member(disp_color_regs, cfg_main, 0x400);
check_member(disp_color_regs, start, 0xC00);
check_member(disp_color_regs, width, 0xC50);
check_member(disp_color_regs, height, 0xC54);
static struct disp_color_regs * const disp_color[2] =
{(void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE};
static struct disp_color_regs *const disp_color[2] = {
(void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE
};
enum {
COLOR_BYPASS_ALL = BIT(7),

12
src/soc/mediatek/mt8173/include/soc/dsi.h
View File

@ -91,8 +91,8 @@ check_member(dsi_regs, dsi_phy_lccon, 0x104);
check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
check_member(dsi_regs, dsi_cmdq0, 0x200);
static struct dsi_regs * const dsi0 = (void *)DSI0_BASE;
static struct dsi_regs * const dsi1 = (void *)DSI1_BASE;
static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
static struct dsi_regs *const dsi1 = (void *)DSI1_BASE;
/* DSI_INTSTA */
enum {
@ -227,8 +227,8 @@ struct mipi_tx_regs {
check_member(mipi_tx_regs, dsi_top_con, 0x40);
check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
static struct mipi_tx_regs * const mipi_tx0 = (void *)MIPI_TX0_BASE;
static struct mipi_tx_regs * const mipi_tx1 = (void *)MIPI_TX0_BASE;
static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE;
/* MIPITX_DSI0_CON */
enum {
@ -322,8 +322,8 @@ struct lvds_tx1_regs {
u32 vopll_ctl3;
};
static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);
static struct lvds_tx1_regs * const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800);
static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);
static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800);
/* LVDS_VOPLL_CTRL3 */
enum {

2
src/soc/mediatek/mt8173/include/soc/flash_controller.h
View File

@ -85,7 +85,7 @@ struct mt8173_nor_regs {
u32 fdma_end_dadr;
};
check_member(mt8173_nor_regs, fdma_end_dadr, 0x724);
static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE;
static struct mt8173_nor_regs *const mt8173_nor = (void *)SFLASH_REG_BASE;
int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash);

2
src/soc/mediatek/mt8173/include/soc/mcucfg.h
View File

@ -102,6 +102,6 @@ struct mt8173_mcucfg_regs {
check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688);
static struct mt8173_mcucfg_regs * const mt8173_mcucfg = (void *)MCUCFG_BASE;
static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
#endif /* __SOC_MEDIATEK_MT8173_MCUCFG_H__ */

2
src/soc/mediatek/mt8173/include/soc/pericfg.h
View File

@ -78,7 +78,7 @@ struct mt8173_pericfg_regs {
u32 ssusb_pdn_sta;
};
static struct mt8173_pericfg_regs * const mt8173_pericfg =
static struct mt8173_pericfg_regs *const mt8173_pericfg =
(void *)PERI_CON_BASE;
/*

2
src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
View File

@ -25,7 +25,7 @@ s32 pwrap_write(u16 adr, u16 wdata);
s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
s32 pwrap_init(void);
static struct mt8173_pwrap_regs * const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
enum {
WACS2 = 1 << 4

2
src/soc/mediatek/mt8173/include/soc/spm.h
View File

@ -154,6 +154,6 @@ struct mt8173_spm_regs {
check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);
static struct mt8173_spm_regs * const mt8173_spm = (void *)SPM_BASE;
static struct mt8173_spm_regs *const mt8173_spm = (void *)SPM_BASE;
#endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */

2
src/soc/mediatek/mt8173/include/soc/timer.h
View File

@ -55,7 +55,7 @@ struct mt8173_gpt_regs {
u32 apxgpt_irqmask1;
};
static struct mt8173_gpt_regs * const mt8173_gpt = (void *)GPT_BASE;
static struct mt8173_gpt_regs *const mt8173_gpt = (void *)GPT_BASE;
enum {
GPT_CON_EN = 0x01,

2
src/soc/mediatek/mt8173/include/soc/usb.h
View File

@ -134,7 +134,7 @@ struct sif_u2_phy_com {
u32 reserved1[17];
u32 u2phydtm0;
u32 u2phydtm1;
u32 reserved2[36]; /* 0x70 - 0xff */
u32 reserved2[36]; /* 0x70 - 0xff */
};
check_member(sif_u2_phy_com, u2phydtm0, 0x68);

2
src/soc/mediatek/mt8173/mt6391.c
View File

@ -152,7 +152,7 @@ static void mt6391_init_setting(void)
mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
udelay(200); /* delay for Buck ready */
udelay(200); /* delay for Buck ready */
/* [3:3]: RG_PWMOC_CK_PDN; For OC protection */
mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);

8
src/soc/mediatek/mt8173/pll.c
View File

@ -328,7 +328,7 @@ void mt_pll_init(void)
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */
udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */
/******************
* xPLL ISO Disable
@ -361,7 +361,7 @@ void mt_pll_init(void)
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].reg, PLL_EN);
udelay(40); /* wait for PLL stable (min delay is 20us) */
udelay(40); /* wait for PLL stable (min delay is 20us) */
/***************
* xPLL DIV RSTB
@ -448,12 +448,12 @@ void mt_pll_enable_ssusb_clk(void)
{
/* set RG_LTECLKSQ_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1);
udelay(100); /* wait for PLL stable */
udelay(100); /* wait for PLL stable */
/* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1);
setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1);
udelay(100); /* wait for PLL stable */
udelay(100); /* wait for PLL stable */
/* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));

4
src/soc/mediatek/mt8173/pmic_wrap.c
View File

@ -88,7 +88,7 @@ static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,
return E_PWR_WAIT_IDLE_TIMEOUT;
} while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
WACS_FSM_IDLE); /* IDLE State */
WACS_FSM_IDLE); /* IDLE State */
if (read_reg)
*read_reg = reg_rdata;
return 0;
@ -108,7 +108,7 @@ static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,
pwrap_err("timeout when waiting for idle\n");
return E_PWR_WAIT_IDLE_TIMEOUT;
}
} while (fp(reg_rdata)); /* IDLE State */
} while (fp(reg_rdata)); /* IDLE State */
if (read_reg)
*read_reg = reg_rdata;
return 0;

6
src/soc/mediatek/mt8173/rtc.c
View File

@ -127,7 +127,7 @@ static int rtc_reg_init(void)
if (!write_trigger())
return 0;
pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
/* init time counters after resetting RTC_DIFF and RTC_CALI */
pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
@ -147,7 +147,7 @@ static int rtc_gpio_init(void)
u16 con;
mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,
MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */
MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */
/* Export 32K clock RTC_32K2V8 */
pwrap_read(RTC_CON, &con);
@ -307,7 +307,7 @@ void rtc_boot(void)
break;
}
pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
pwrap_read(RTC_BBPU, &bbpu);
pwrap_read(RTC_CON, &con);

16
src/soc/mediatek/mt8173/uart.c
View File

@ -86,10 +86,10 @@ static int mtk_uart_tst_byte(void);
static void mtk_uart_init(void)
{
/* Use a hardcoded divisor for now. */
const unsigned uartclk = 26 * MHz;
const unsigned baudrate = get_uart_baudrate();
const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */
unsigned highspeed, quot, divisor, remainder;
const unsigned int uartclk = 26 * MHz;
const unsigned int baudrate = get_uart_baudrate();
const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */
unsigned int highspeed, quot, divisor, remainder;
if (baudrate <= 115200) {
highspeed = 0;
@ -124,19 +124,21 @@ static void mtk_uart_init(void)
/* Enable FIFOs, and clear receive and transmit. */
write8(&uart_ptr->fcr,
UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
UART8250_FCR_CLEAR_XMIT);
UART8250_FCR_CLEAR_XMIT);
}
static void mtk_uart_tx_byte(unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
;
write8(&uart_ptr->thr, data);
}
static void mtk_uart_tx_flush(void)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
;
}
static unsigned char mtk_uart_rx_byte(void)

2
src/soc/mediatek/mt8173/wdt.c
View File

@ -20,7 +20,7 @@
#include <soc/wdt.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE;
static struct mt8173_wdt_regs *const mt8173_wdt = (void *)RGU_BASE;
int mtk_wdt_init(void)
{