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mb/google/mancomb: Delete board support 

Mancomb mainboard has been cancelled. Hence delete the board support.

BUG=b:190404616
TEST=None

Cq-Depend: chromium:3188634
Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-09-27 16:26:29 -06:00 committed by Felix Held
parent ea5c31138b
commit f42fca18cb
23 changed files with 0 additions and 1195 deletions
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99
src/mainboard/google/mancomb/Kconfig
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@ -1,99 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
config BOARD_GOOGLE_BASEBOARD_MANCOMB
def_bool n
if BOARD_GOOGLE_BASEBOARD_MANCOMB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_AMD_I2S_MACHINE_DEV
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_UART_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SKUID
select ELOG
select ELOG_GSMI
select FW_CONFIG
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select HAVE_ACPI_RESUME
select HAVE_EM100_SUPPORT
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PSP_DISABLE_POSTCODES
select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI
config CHROMEOS
select EC_GOOGLE_CHROMEEC_SWITCHES
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_STARTS_IN_BOOTBLOCK
config VBOOT_VBNV_OFFSET
hex
default 0x2A
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
config MAINBOARD_DIR
default "google/mancomb"
config MAINBOARD_PART_NUMBER
default "Mancomb" if BOARD_GOOGLE_MANCOMB
config AMD_FWM_POSITION_INDEX
int
default 3
help
TODO: might need to be adapted for better placement of files in cbfs
config DRIVER_TPM_I2C_BUS
hex
default 0x03
config DRIVER_TPM_I2C_ADDR
hex
default 0x50
config AMDFW_CONFIG_FILE
string
default "src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg"
config EFS_SPI_READ_MODE
int
default 0 if EM100 # Normal read mode
default 4 # Dual IO (1-2-2)
config EFS_SPI_SPEED
int
default 3 if EM100 # 16.66 MHz
default 1 # 33.33 MHz
config VARIANT_DIR
default "mancomb" if BOARD_GOOGLE_MANCOMB
config DEVICETREE
default "variants/baseboard/devicetree.cb"
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_FAMILY
string
default "Google_Mancomb"
endif # BOARD_GOOGLE_BASEBOARD_MANCOMB

5
src/mainboard/google/mancomb/Kconfig.name
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comment "Mancomb"
config BOARD_GOOGLE_MANCOMB
bool "-> Mancomb"
select BOARD_GOOGLE_BASEBOARD_MANCOMB

25
src/mainboard/google/mancomb/Makefile.inc
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@ -1,25 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),)
$(info APCB sources present.)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
else
$(info APCB sources not found. Skipping APCB.)
endif
bootblock-y += bootblock.c
verstage-y += verstage.c
romstage-y += port_descriptors.c
ramstage-y += ec.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
subdirs-y += variants/baseboard
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

6
src/mainboard/google/mancomb/board_info.txt
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@ -1,6 +0,0 @@
Vendor name: Google
Board name: Mancomb
Category: desktop
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

37
src/mainboard/google/mancomb/bootblock.c
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@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
void bootblock_mainboard_early_init(void)
{
size_t num_gpios;
uint32_t dword;
const struct soc_amd_gpio *gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
gpios = variant_early_gpio_table(&num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
dword = pm_read32(0x90);
dword |= 1 << 16;
pm_write32(0x90, dword);
dword = pm_read32(0x74);
dword |= 3 << 10;
pm_write32(0x74, dword);
}

24
src/mainboard/google/mancomb/chromeos.c
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, 0, "power"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

33
src/mainboard/google/mancomb/chromeos.fmd
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@ -1,33 +0,0 @@
FLASH@0xFF000000 16M {
SI_BIOS {
RW_MRC_CACHE(PRESERVE) 64K
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 4K
RW_LEGACY(CBFS)
WP_RO@8M 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 12K
COREBOOT(CBFS)
}
}
}
}

27
src/mainboard/google/mancomb/dsdt.asl
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@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <variant/ec.h>
DefinitionBlock (
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001 /* OEM Revision */
)
{
#include <acpi/dsdt_top.asl>
#include <soc.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
}

33
src/mainboard/google/mancomb/ec.c
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@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <amdblocks/gpio.h>
#include <amdblocks/smi.h>
#include <ec/google/chromeec/ec.h>
#include <soc/smi.h>
#include <variant/ec.h>
static const struct sci_source espi_sci_sources[] = {
{
.scimap = SMITYPE_ESPI_SCI_B,
.gpe = EC_SCI_GPI,
.direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */
.level = SMI_SCI_EDG, /* enum smi_sci_dir */
}
};
void mainboard_ec_init(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
};
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
/* Configure eSPI VW SCI events */
gpe_configure_sci(espi_sci_sources, ARRAY_SIZE(espi_sci_sources));
}

119
src/mainboard/google/mancomb/mainboard.c
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@ -1,119 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/device.h>
#include <soc/acpi.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
/*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
* This table is responsible for physically routing the PIC and
* IOAPIC IRQs to the different PCI devices on the system. It
* is read and written via registers 0xC00/0xC01 as an
* Index/Data pair. These values are chipset and mainboard
* dependent and should be updated accordingly.
*/
static uint8_t fch_pic_routing[0x80];
static uint8_t fch_apic_routing[0x80];
_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
"PIC and APIC FCH interrupt tables must be the same size");
/*
* This controls the device -> IRQ routing.
*
* Hardcoded IRQs:
* 0: timer < soc/amd/common/acpi/lpc.asl
* 1: i8042 - Keyboard
* 2: cascade
* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
* 9: acpi <- soc/amd/common/acpi/lpc.asl
*/
static const struct fch_irq_routing {
uint8_t intr_index;
uint8_t pic_irq_num;
uint8_t apic_irq_num;
} guybrush_fch[] = {
{ PIRQ_A, PIRQ_NC, PIRQ_NC },
{ PIRQ_B, PIRQ_NC, PIRQ_NC },
{ PIRQ_C, PIRQ_NC, PIRQ_NC },
{ PIRQ_D, PIRQ_NC, PIRQ_NC },
{ PIRQ_E, PIRQ_NC, PIRQ_NC },
{ PIRQ_F, PIRQ_NC, PIRQ_NC },
{ PIRQ_G, PIRQ_NC, PIRQ_NC },
{ PIRQ_H, PIRQ_NC, PIRQ_NC },
{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
{ PIRQ_SATA, PIRQ_NC, PIRQ_NC },
{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
{ PIRQ_GPIO, 11, 11 },
{ PIRQ_I2C0, 10, 10 },
{ PIRQ_I2C1, 7, 7 },
{ PIRQ_I2C2, 6, 6 },
{ PIRQ_I2C3, 5, 5 },
{ PIRQ_UART0, 4, 4 },
{ PIRQ_UART1, 3, 3 },
/* The MISC registers are not interrupt numbers */
{ PIRQ_MISC, 0xfa, 0x00 },
{ PIRQ_MISC0, 0x91, 0x00 },
{ PIRQ_HPET_L, 0x00, 0x00 },
{ PIRQ_HPET_H, 0x00, 0x00 },
};
static void init_tables(void)
{
const struct fch_irq_routing *entry;
int i;
memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
for (i = 0; i < ARRAY_SIZE(guybrush_fch); i++) {
entry = guybrush_fch + i;
fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
}
}
static void pirq_setup(void)
{
intr_data_ptr = fch_apic_routing;
picr_data_ptr = fch_pic_routing;
}
static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios;
base_gpios = variant_base_gpio_table(&base_num_gpios);
override_gpios = variant_override_gpio_table(&override_num_gpios);
gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
override_num_gpios);
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
init_tables();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

121
src/mainboard/google/mancomb/port_descriptors.c
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@ -1,121 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/platform_descriptors.h>
#include <soc/gpio.h>
#include <types.h>
static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
{ /* WLAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.gpio_group_id = GPIO_29,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* SD */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ1,
.gpio_group_id = GPIO_70,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* LAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 2,
.end_logical_lane = 2,
.device_number = 2,
.function_number = 3,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2,
.gpio_group_id = GPIO_18,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* NVME */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 4,
.end_logical_lane = 7,
.device_number = 2,
.function_number = 4,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
.gpio_group_id = GPIO_40,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* TODO: remove this temporay workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 8,
.end_logical_lane = 11,
.device_number = 2,
.function_number = 5,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ5,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* TODO: remove this temporay workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 23,
.device_number = 1,
.function_number = 1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ6,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
}
};
/* TODO: verify the DDI table, since this is mostly an educated guess right now */
static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = {
{ /* DDI0 - DP */
.connector_type = DDI_DP,
.aux_index = DDI_AUX1,
.hdp_index = DDI_HDP1
},
{ /* DDI1 - HDMI */
.connector_type = DDI_HDMI,
.aux_index = DDI_AUX2,
.hdp_index = DDI_HDP2
},
{ /* DDI2 */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI3 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI4 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX4,
.hdp_index = DDI_HDP4,
}
};
void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
*dxio_descs = mancomb_czn_dxio_descriptors;
*dxio_num = ARRAY_SIZE(mancomb_czn_dxio_descriptors);
*ddi_descs = mancomb_czn_ddi_descriptors;
*ddi_num = ARRAY_SIZE(mancomb_czn_ddi_descriptors);
}

38
src/mainboard/google/mancomb/smihandler.c
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@ -1,38 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <variant/ec.h>
void mainboard_smi_gpi(u32 gpi_sts)
{
printk(BIOS_WARNING, "No GPIO is set up as PAD_SMI, so %s should never end up being "
"called. gpi_status is %x.\n", __func__, gpi_sts);
}
void mainboard_smi_sleep(u8 slp_typ)
{
size_t num_gpios;
const struct soc_amd_gpio *gpios;
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
gpios = variant_sleep_gpio_table(&num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
int mainboard_smi_apmc(u8 apmc)
{
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
return 0;
}
void elog_gsmi_cb_mainboard_log_wake_source(void)
{
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
}

11
src/mainboard/google/mancomb/variants/baseboard/Makefile.inc
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@ -1,11 +0,0 @@
bootblock-y += gpio.c
romstage-y += tpm_tis.c
ramstage-y += gpio.c
ramstage-y += tpm_tis.c
verstage-y += gpio.c
verstage-y += tpm_tis.c
smm-y += gpio.c

40
src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg
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@ -1,40 +0,0 @@
# PSP fw config file
FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP
# type file
# PSP
AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn
PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin
PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin
PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin
PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin
PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin
PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn
PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin
PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin
PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin
PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin
PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin
PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin
PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin
AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin
PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN.csbin
VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin
SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin
UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin
DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin
KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin
KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin
DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin
DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin
PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin
# BDT
PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
PSP_MP2CFG_FILE MP2FWConfig.sbin

156
src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
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@ -1,156 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne
register "common_config.acp_config" = "{
.acp_pin_cfg = I2S_PINS_I2S_TDM,
.acp_i2s_wake_enable = 0,
.acp_pme_enable = 0,
}"
register "system_configuration" = "3"
# eSPI Configuration
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
.generic_io_range[0] = {
.base = 0x62,
/*
* Only 0x62 and 0x66 are required. But, this is not supported by
* standard IO decodes and there are only 4 generic I/O windows
* available. Hence, open a window from 0x62-0x67.
*/
.size = 5,
},
.generic_io_range[1] = {
.base = 0x800, /* EC_HOST_CMD_REGION0 */
.size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */
},
.generic_io_range[2] = {
.base = 0x900, /* EC_LPC_ADDR_MEMMAP */
.size = 255, /* EC_MEMMAP_SIZE */
},
.generic_io_range[3] = {
.base = 0x200, /* EC_LPC_ADDR_HOST_DATA */
.size = 8, /* 0x200 - 0x207 */
},
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_IN_BAND,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 0,
.flash_ch_en = 0,
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
# Enable S0i3 support
register "s0ix_enable" = "1"
register "pspp_policy" = "DXIO_PSPP_BALANCED"
device domain 0 on
device ref gpp_bridge_0 on end # WLAN
device ref gpp_bridge_1 on end # SD
device ref gpp_bridge_2 on end # LAN
device ref gpp_bridge_3 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # GFX HD Audio Controller
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
device ref xhci_0_root_hub on
chip drivers/usb/acpi
register "desc" = ""Rear Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""Front Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""Rear Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""Front Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb2_port1 on end
end
end
end
end
device ref xhci_1 on # USB 3.1 (USB1)
chip drivers/usb/acpi
device ref xhci_1_root_hub on
chip drivers/usb/acpi
register "desc" = ""Front Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb3_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB HUB""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb3_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""Front Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB HUB""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)"
device ref usb2_port6 on end
end
end
end
end
device ref acp on
chip drivers/amd/i2s_machine_dev
register "hid" = ""10025682""
device generic 0.0 on end
end
end # Audio
end
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
end # domain
device ref i2c_3 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "desc" = ""Cr50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
device i2c 50 on end
end
end
device ref uart_0 on end # UART0
end # chip soc/amd/cezanne

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src/mainboard/google/mancomb/variants/baseboard/gpio.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* GPIO configuration in ramstage*/
static const struct soc_amd_gpio base_gpio_table[] = {
/* PWR_BTN_L */
PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
/* SYS_RESET_L */
PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
/* WAKE_L */
PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
/* GSC_SOC_INT_L */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* AGPIO4 */
PAD_NC(GPIO_4),
/* AGPIO5 */
PAD_NC(GPIO_5),
/* EN_PP3300_WLAN */
PAD_GPO(GPIO_6, HIGH),
/* AGPIO7 */
PAD_NC(GPIO_7),
/* EN_PP3300_LAN */
PAD_GPO(GPIO_8, LOW),
/* SD_EX_PRSNT_L */
PAD_GPI(GPIO_9, PULL_NONE),
/* S0A3 */
PAD_NF(GPIO_10, S0A3, PULL_NONE),
/* AGPIO11 */
PAD_NC(GPIO_11),
/* SLP_S3_GATED */
PAD_GPO(GPIO_12, LOW),
/* GPIO_13 - GPIO_15: Not available */
/* USB_FAULT_ODL */
PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
/* AGPIO17 */
PAD_NC(GPIO_17),
/* LAN_AUX_RESET_L */
PAD_GPO(GPIO_18, LOW),
/* I2C3_SCL */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* AGPIO21 */
PAD_NC(GPIO_21),
/* EC_SOC_WAKE_ODL */
PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW),
/* AC_PRES */
PAD_NF(GPIO_23, AC_PRES, PULL_UP),
/* HUB_RST_L */
PAD_GPO(GPIO_24, HIGH),
/* GPIO_25: Not available */
/* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */
PAD_GPO(GPIO_26, HIGH),
/* PCIE_RST1_L */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* GPIO_28: Not available */
/* WLAN_AUX_RESET */
PAD_GPO(GPIO_29, LOW),
/* ESPI_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* AGPIO31 */
PAD_NC(GPIO_31),
/* AGPIO32 */
PAD_NC(GPIO_32),
/* GPIO_33 - GPIO_39: Not available */
/* SSD_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH),
/* GPIO_41: Not available */
/* EGPIO42 */
PAD_NC(GPIO_42),
/* GPIO_43 - GPIO_66: Not available */
/* SOC_BIOS_WP_L */
PAD_GPI(GPIO_67, PULL_NONE),
/* AGPIO68 */
PAD_NC(GPIO_68),
/* AGPIO69 */
PAD_NC(GPIO_69),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_70, HIGH),
/* GPIO_71 - GPIO_73: Not available */
/* EGPIO74 */
PAD_NC(GPIO_74),
/* EGPIO75 */
PAD_NC(GPIO_75),
/* EGPIO76 */
PAD_NC(GPIO_76),
/* GPIO_77 - GPIO_83: Not available */
/* EC_SOC_INT_ODL */
PAD_GPI(GPIO_84, PULL_NONE),
/* AGPIO85 */
PAD_NC(GPIO_85),
/* ESPI_SOC_CLK */
PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
/* AGPIO87 */
PAD_NC(GPIO_87),
/* AGPIO88 */
PAD_NC(GPIO_88),
/* AGPIO89 */
PAD_NC(GPIO_89),
/* HP_INT_ODL */
PAD_GPI(GPIO_90, PULL_NONE),
/* PWM_3V3_BUZZER */
PAD_GPO(GPIO_91, LOW),
/* CLK_REQ0_L */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
/* GPIO_93 - GPIO_103: Not available */
/* ESPI1_DATA0 */
PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
/* EGPIO109 */
PAD_NC(GPIO_109),
/* GPIO_110 - GPIO_112: Not available */
/* I2C2_SCL */
PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
/* I2C2_SDA */
PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
/* CLK_REQ1_L */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
/* CLK_REQ2_L */
PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
/* GPIO_117 - GPIO_119: Not available */
/* EGPIO120 */
PAD_NC(GPIO_120),
/* EGPIO121 */
PAD_NC(GPIO_121),
/* GPIO_122 - GPIO_128: Not available */
/* AGPIO129 */
PAD_NC(GPIO_129),
/* WLAN_DISABLE */
PAD_GPO(GPIO_130, LOW),
/* CLK_REQ3_L */
PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE),
/* BT_DISABLE */
PAD_GPO(GPIO_132, LOW),
/* EGPIO140 */
PAD_NC(GPIO_140),
/* UART0_RXD */
PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
/* EGPIO142 */
PAD_NC(GPIO_142),
/* UART0_TXD */
PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
/* AGPIO144 */
PAD_NC(GPIO_144),
/* I2C0_SCL */
PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
/* I2C0_SDA */
PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
/* I2C1_SCL */
PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
/* I2C1_SDA */
PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
};
/* Early GPIO configuration */
static const struct soc_amd_gpio early_gpio_table[] = {
/* EN_PP3300_WLAN */
PAD_GPO(GPIO_6, HIGH),
/* WLAN_DISABLE */
PAD_GPO(GPIO_130, LOW),
/* GSC_SOC_INT_L */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* I2C3_SCL */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* PCIE_RST0_L */
PAD_GPO(GPIO_26, HIGH),
/* ESPI_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* ESPI_SOC_CLK */
PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
/* ESPI1_DATA0 */
PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
/* UART0_RXD */
PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
/* UART0_TXD */
PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
};
/* GPIO configuration for sleep */
static const struct soc_amd_gpio sleep_gpio_table[] = {
/* TODO: Fill sleep gpio configuration */
};
const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(base_gpio_table);
return base_gpio_table;
}
const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size)
{
*size = 0;
return NULL;
}
const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}

59
src/mainboard/google/mancomb/variants/baseboard/include/baseboard/ec.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_EC_H__
#define __MAINBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#include <soc/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)
/* EC can wake from S3 with lid, power button or mode change event */
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Set GPI for SCI */
#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
/* Enable EC sync interrupt */
#define EC_ENABLE_SYNC_IRQ_GPIO
/* EC sync irq */
#define EC_SYNC_IRQ GPIO_84
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
#endif /* __MAINBOARD_EC_H__ */

11
src/mainboard/google/mancomb/variants/baseboard/include/baseboard/gpio.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
#include <soc/gpio.h>
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_67
#endif /* __BASEBOARD_GPIO_H__ */

27
src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
#include <amdblocks/gpio.h>
/*
* This function provides base GPIO configuration table. It is typically provided by
* baseboard using a weak implementation. If GPIO configuration for a variant differs
* significantly from the baseboard, then the variant can also provide a strong implementation
* of this function.
*/
const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
/*
* This function allows variant to override any GPIOs that are different than the base GPIO
* configuration provided by variant_base_gpio_table().
*/
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
/* This function provides early GPIO init in bootblock or psp. */
const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
/* This function provides GPIO settings before entering sleep. */
const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);
#endif /* __BASEBOARD_VARIANTS_H__ */

9
src/mainboard/google/mancomb/variants/baseboard/tpm_tis.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <security/tpm/tis.h>
#include <soc/gpio.h>
int tis_plat_irq_status(void)
{
return gpio_interrupt_status(GPIO_3);
}

3
src/mainboard/google/mancomb/variants/mancomb/include/variant/ec.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/ec.h>

64
src/mainboard/google/mancomb/variants/mancomb/overridetree.cb
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# SPDX-License-Identifier: GPL-2.0-or-later
fw_config
field WLAN 0 1
option WLAN_WCN6856 0
option WLAN_RTL8852 1
end
field BEEP_MODE 2 3
option BEEP_MODE_PIEZO 0
option BEEP_MODE_AMP 1
option BEEP_MODE_BIT_BANG 2
end
field SOC_TDP 4 5
option TDP_25_WATTS 0
option TDP_15_WATTS 1
end
end
chip soc/amd/cezanne
register "slow_ppt_limit_mW" = "37500"
register "fast_ppt_limit_mW" = "48000"
register "slow_ppt_time_constant_s" = "5"
register "stapm_time_constant_s" = "275"
register "sustained_power_limit_mW" = "25000"
register "thermctl_limit_degreeC" = "100"
device domain 0 on
end # domain
# I2C Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | memory SPD bus |
#| I2C2 | Codec |
#| I2C3 | H1/D2 TPM |
#+-------------------+---------------------------+
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.early_init = true,
}"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
}"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.early_init = true,
}"
device ref i2c_2 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end # I2C2
end # chip soc/amd/cezanne

24
src/mainboard/google/mancomb/verstage.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/gpio.h>
#include <baseboard/variants.h>
#include <security/vboot/vboot_common.h>
static void setup_gpio(void)
{
const struct soc_amd_gpio *gpios;
size_t num_gpios;
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
gpios = variant_early_gpio_table(&num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
}
void verstage_mainboard_early_init(void)
{
setup_gpio();
}
void verstage_mainboard_init(void)
{
}