libpayload: remove uhci_reg_maskX
Not that good an idea to start with. Coccinelle patch: @@ @@ -void ( -uhci_reg_mask8 | -uhci_reg_mask16 | -uhci_reg_mask32 ) - (...) { ... } @@ @@ -void ( -uhci_reg_mask8 | -uhci_reg_mask16 | -uhci_reg_mask32 ) - (...); @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask32 (ctrl, reg, ~0, ormask) +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask) @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask16 (ctrl, reg, ~0, ormask) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask) @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask8 (ctrl, reg, ~0, ormask) +uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask32 (ctrl, reg, andmask, 0) +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask16 (ctrl, reg, andmask, 0) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask16 (ctrl, reg, andmask, 0) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask) Change-Id: Id0eb8327293831e54249d43fd06d50963c793699 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/477 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -120,7 +120,8 @@ uhci_reset (hci_t *controller)
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/* reset framelist index */
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uhci_reg_write16 (controller, FRNUM, 0);
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uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0); // max packets, configure flag
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) | 0xc0); // max packets, configure flag
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uhci_start (controller);
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}
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@ -240,7 +241,8 @@ uhci_shutdown (hci_t *controller)
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detach_controller (controller);
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UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
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roothub);
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uhci_reg_mask16 (controller, USBCMD, 0, 0); // stop work
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) & 0); // stop work
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free (UHCI_INST (controller)->framelistptr);
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free (UHCI_INST (controller)->qh_prei);
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free (UHCI_INST (controller)->qh_intr);
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@ -253,13 +255,15 @@ uhci_shutdown (hci_t *controller)
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static void
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uhci_start (hci_t *controller)
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{
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uhci_reg_mask16 (controller, USBCMD, ~0, 1); // start work on schedule
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) | 1); // start work on schedule
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}
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static void
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uhci_stop (hci_t *controller)
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{
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uhci_reg_mask16 (controller, USBCMD, ~1, 0); // stop work on schedule
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) & ~1); // stop work on schedule
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}
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#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
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@ -274,7 +278,8 @@ wait_for_completed_qh (hci_t *controller, qh_t *qh)
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current = GET_TD (qh->elementlinkptr.ptr);
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timeout = 1000000;
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}
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uhci_reg_mask16 (controller, USBSTS, ~0, 0); // clear resettable registers
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uhci_reg_write16(controller, USBSTS,
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uhci_reg_read16(controller, USBSTS) | 0); // clear resettable registers
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udelay (30);
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}
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return (GET_TD (qh->elementlinkptr.ptr) ==
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@ -636,24 +641,3 @@ uhci_reg_read8 (hci_t *ctrl, usbreg reg)
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{
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return inb (ctrl->reg_base + reg);
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}
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void
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uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
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{
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uhci_reg_write32 (ctrl, reg,
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(uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
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}
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void
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uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
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{
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uhci_reg_write16 (ctrl, reg,
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(uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
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}
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void
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uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
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{
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uhci_reg_write8 (ctrl, reg,
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(uhci_reg_read8 (ctrl, reg) & andmask) | ormask);
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}
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@ -104,9 +104,6 @@ typedef struct {
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u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg);
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void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value);
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u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg);
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void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask);
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void uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask);
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void uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask);
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typedef struct uhci {
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flistp_t *framelistptr;
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@ -53,14 +53,18 @@ uhci_rh_enable_port (usbdev_t *dev, int port)
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return;
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}
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uhci_reg_mask16 (controller, port, ~(1 << 12), 0); /* wakeup */
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uhci_reg_write16(controller, port,
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uhci_reg_read16(controller, port) & ~(1 << 12)); /* wakeup */
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uhci_reg_mask16 (controller, port, ~0, 1 << 9); /* reset */
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uhci_reg_write16(controller, port,
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uhci_reg_read16(controller, port) | 1 << 9); /* reset */
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mdelay (30); // >10ms
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uhci_reg_mask16 (controller, port, ~(1 << 9), 0);
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uhci_reg_write16(controller, port,
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uhci_reg_read16(controller, port) & ~(1 << 9));
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mdelay (1); // >5.3us per spec, <3ms because some devices make trouble
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uhci_reg_mask16 (controller, port, ~0, 1 << 2); /* enable */
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uhci_reg_write16(controller, port,
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uhci_reg_read16(controller, port) | 1 << 2); /* enable */
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do {
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value = uhci_reg_read16 (controller, port);
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mdelay (1);
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@ -75,7 +79,8 @@ uhci_rh_disable_port (usbdev_t *dev, int port)
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port = PORTSC2;
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if (port == 1)
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port = PORTSC1;
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uhci_reg_mask16 (controller, port, ~4, 0);
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uhci_reg_write16(controller, port,
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uhci_reg_read16(controller, port) & ~4);
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int value;
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do {
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value = uhci_reg_read16 (controller, port);
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@ -102,7 +107,8 @@ uhci_rh_scanport (usbdev_t *dev, int port)
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usb_detach_device(dev->controller, devno);
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RH_INST (dev)->port[offset] = -1;
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}
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uhci_reg_mask16 (dev->controller, portsc, ~0, (1 << 3) | (1 << 2)); // clear port state change, enable port
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uhci_reg_write16(dev->controller, portsc,
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uhci_reg_read16(dev->controller, portsc) | (1 << 3) | (1 << 2)); // clear port state change, enable port
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mdelay(100); // wait for signal to stabilize
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