diff --git a/src/northbridge/motorola/mpc107/meminfo.c b/src/northbridge/motorola/mpc107/meminfo.c
index c7df85d617..20c95e3aad 100644
--- a/src/northbridge/motorola/mpc107/meminfo.c
+++ b/src/northbridge/motorola/mpc107/meminfo.c
@@ -22,7 +22,7 @@
 #include "mpc107.h"
 
 void 
-sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
+sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm)
 {
     sdram_bank_info *bank1 = dimm->bank1;
     sdram_bank_info *bank2 = dimm->bank2;
@@ -38,8 +38,7 @@ sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
 
     if (data[0] < 64)
     {
-	if (verbose)
-	    printk_info("SPD data too short\n");
+	printk_info("SPD data too short\n");
 	return;
     }
 
@@ -48,15 +47,13 @@ sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
 
     if (csum != data[63])
     {
-	if (verbose)
-	    printk_info("Broken checksum 0x%x, should be 0x%x\n", data[63], csum);
+	printk_info("Broken checksum 0x%x, should be 0x%x\n", data[63], csum);
 	return;
     }
     
     if (data[2] != 0x04)
     {
-	if (verbose)
-	    printk_info("SDRAM Only\n");
+	printk_info("SDRAM Only\n");
 	return;
     }
     
@@ -76,15 +73,13 @@ sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
     
     if (data[7] || (data[6] != 80 && data[6] != 72 && data[6] != 64))
     {
-	if (verbose)
-	    printk_info("Data width incorrect\n");
+	printk_info("Data width incorrect\n");
 	return;
     }
     
     if (data[8] != 0x01)
     {
-	if (verbose)
-	    printk_info("3.3V TTL DIMMS only\n");
+	printk_info("3.3V TTL DIMMS only\n");
 	return;
     }
     
@@ -138,11 +133,11 @@ sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
 	    bank2->access_time[no_cas_latencies - 3] =
 		100 * (data[26] >> 2) + 25 * (data[26] & 0x3);
     }
-    if (verbose)
-    	for(i = 0; i < no_cas_latencies; i++)
-	    printk_info("CL %d: cycle %dns access %dns\n",
-		bank1->cas_latency[i], bank1->cycle_time[i] / 100,
-		bank1->access_time[i] / 100);
+
+    for(i = 0; i < no_cas_latencies; i++)
+	printk_debug("CL %d: cycle %dns access %dns\n",
+	    bank1->cas_latency[i], bank1->cycle_time[i] / 100,
+	    bank1->access_time[i] / 100);
 
     /* Other timings */
     bank1->min_back_to_back = bank2->min_back_to_back = data[15];
@@ -182,7 +177,8 @@ sdram_dimm_to_bank_info(const char *data,  sdram_dimm_info *dimm, int verbose)
 void 
 print_sdram_bank_info(const sdram_bank_info *bank)
 {
-    printk_info("Bank %d: %dMB\n", bank->number, bank->size / (1024*1024));
+    if (bank->size)
+	printk_debug("  Bank %d: %dMB\n", bank->number, bank->size / (1024*1024));
 }
 
 static const char *error_types[] = {"", "Parity ", "ECC "};
@@ -190,13 +186,15 @@ static const char *error_types[] = {"", "Parity ", "ECC "};
 void 
 print_sdram_dimm_info(const sdram_dimm_info *dimm)
 {
-    printk_info("Dimm %d: ", dimm->number);
-    if (dimm->size)
-    	printk_info("%dMB CL%d (%s): Running at CL%d %s\n", 
+    printk_debug("Dimm %d: ", dimm->number);
+    if (dimm->size) {
+    	printk_debug("%dMB CL%d (%s): Running at CL%d %s\n", 
 	     dimm->size / (1024*1024), dimm->bank1->cas_latency[0],
 	     dimm->part_number,
 	     dimm->bank1->actual_cas,
 	     error_types[dimm->bank1->actual_detect]);
-    else
-	printk_info("(none)\n");
+	print_sdram_bank_info(dimm->bank1);
+	print_sdram_bank_info(dimm->bank2);
+    } else
+	printk_debug("(none)\n");
 }
diff --git a/src/northbridge/motorola/mpc107/mpc107.c b/src/northbridge/motorola/mpc107/mpc107.c
index ec91a675d7..fbda7f9079 100644
--- a/src/northbridge/motorola/mpc107/mpc107.c
+++ b/src/northbridge/motorola/mpc107/mpc107.c
@@ -36,12 +36,20 @@ void mpc107_init(void);
 void 
 memory_init(void)
 {
+	unsigned dimm;
+	uint32_t mem_size;
+ 
 	struct sdram_dimm_info dimms[NUM_DIMMS];
 	struct sdram_bank_info banks[NUM_BANKS];
 
 	mpc107_init();
 	mpc107_probe_dimms(NUM_DIMMS, dimms, banks);
-	(void)mpc107_config_memory(NUM_BANKS, banks, 2);
+	mem_size = mpc107_config_memory(NUM_BANKS, banks, 2);
+	
+	for (dimm = 0; dimm < NUM_DIMMS; dimm ++)
+		print_sdram_dimm_info(&dimms[dimm]);
+
+	printk_info("Configured %dMB memory\n", mem_size / (1024*1024));
 }
 
 /*
@@ -290,7 +298,7 @@ mpc107_init(void)
  * Configure real memory settings.
  */
 unsigned long 
-mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
+mpc107_config_memory(int no_banks, sdram_bank_info *bank, int for_real)
 {
 	int i, j;
 	char ignore[8];
@@ -314,7 +322,9 @@ mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
 	uint32_t extmemstart1, extmemstart2;
 	uint32_t memend1, memend2;
 	uint32_t extmemend1, extmemend2;
-	uint32_t address;
+	uint32_t mem_size;
+
+	printk_debug("Configuring DIMMS...\n");
 
 	/* Set up the ignore mask */
 	for(i = 0; i < no_banks; i++)
@@ -453,7 +463,7 @@ mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
 	mccr2 |= refint << 2;
 	mccr1 |= 0x00080000;	/* memgo */
 
-	address = 0;
+	mem_size = 0;
 	memstart1 = memstart2 = 0;
 	extmemstart1 = extmemstart2 = 0;
 	memend1 = memend2 = 0;
@@ -461,21 +471,21 @@ mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
 	bank_enable = 0;
 	for (i = 0; i < no_banks; i++) {
 		if (! ignore[i]) {
-			uint32_t end = address + bank[i].size - 1;
+			uint32_t end = mem_size + bank[i].size - 1;
 			bank_enable |= 1 << i;
 			if (i < 4) {
-				memstart1 |= ((address >> 20) & 0xff) << (8 * i);
-				extmemstart1 |= ((address >> 28) & 0x03) << (8 * i);
+				memstart1 |= ((mem_size >> 20) & 0xff) << (8 * i);
+				extmemstart1 |= ((mem_size >> 28) & 0x03) << (8 * i);
 				memend1 |= ((end >> 20) & 0xff) << (8 * i);
 				extmemend1 |= ((end >> 28) & 0x03) << (8 * i);
 			} else {
 				int k = i - 4;
-				memstart2 |= ((address >> 20) & 0xff) << (8 * k);
-				extmemstart2 |= ((address >> 28) & 0x03) << (8 * k);
+				memstart2 |= ((mem_size >> 20) & 0xff) << (8 * k);
+				extmemstart2 |= ((mem_size >> 28) & 0x03) << (8 * k);
 				memend2 |= ((end >> 20) & 0xff) << (8 * k);
 				extmemend2 |= ((end >> 28) & 0x03) << (8 * k);
 			}
-			address += bank[i].size;
+			mem_size += bank[i].size;
 		}
 	}
 
@@ -484,33 +494,34 @@ mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
 		/*
 		 * Mask MEMGO bit before setting MCCR1
 		 */
+		printk_debug("Setting memory configuration registers...\n");
 		mccr1 &= ~0x80000;
-		printk_info("MCCR1 = 0x%08x\n", mccr1);
+		printk_debug("  MCCR1 = 0x%08x\n", mccr1);
 		pci_ppc_write_config32(0, 0, 0xf0, mccr1);
 
-		printk_info("MBEN = 0x%02x\n", bank_enable);
+		printk_debug("  MBEN = 0x%02x\n", bank_enable);
 		pci_ppc_write_config8(0, 0, 0xa0, bank_enable);
-		printk_info("MSAR1 = 0x%08x\n", memstart1);
+		printk_debug("  MSAR1 = 0x%08x\n", memstart1);
 		pci_ppc_write_config32(0, 0, 0x80, memstart1);
-		printk_info("MSAR2 = 0x%08x\n", memstart2);
+		printk_debug("  MSAR2 = 0x%08x\n", memstart2);
 		pci_ppc_write_config32(0, 0, 0x84, memstart2);
-		printk_info("MSAR3 = 0x%08x\n", extmemstart1);
+		printk_debug("  MSAR3 = 0x%08x\n", extmemstart1);
 		pci_ppc_write_config32(0, 0, 0x88, extmemstart1);
-		printk_info("MSAR4 = 0x%08x\n", extmemstart2);
+		printk_debug("  MSAR4 = 0x%08x\n", extmemstart2);
 		pci_ppc_write_config32(0, 0, 0x8c, extmemstart2);
-		printk_info("MEAR1 = 0x%08x\n", memend1);
+		printk_debug("  MEAR1 = 0x%08x\n", memend1);
 		pci_ppc_write_config32(0, 0, 0x90, memend1);
-		printk_info("MEAR2 = 0x%08x\n", memend2);
+		printk_debug("  MEAR2 = 0x%08x\n", memend2);
 		pci_ppc_write_config32(0, 0, 0x94, memend2);
-		printk_info("MEAR3 = 0x%08x\n", extmemend1);
+		printk_debug("  MEAR3 = 0x%08x\n", extmemend1);
 		pci_ppc_write_config32(0, 0, 0x98, extmemend1);
-		printk_info("MEAR4 = 0x%08x\n", extmemend2);
+		printk_debug("  MEAR4 = 0x%08x\n", extmemend2);
 		pci_ppc_write_config32(0, 0, 0x9c, extmemend2);
-		printk_info("MCCR2 = 0x%08x\n", mccr2);
+		printk_debug("  MCCR2 = 0x%08x\n", mccr2);
 		pci_ppc_write_config32(0, 0, 0xf4, mccr2);
-		printk_info("MCCR3 = 0x%08x\n", mccr3);
+		printk_debug("  MCCR3 = 0x%08x\n", mccr3);
 		pci_ppc_write_config32(0, 0, 0xf8, mccr3);
-		printk_info("MCCR4 = 0x%08x\n", mccr4);
+		printk_debug("  MCCR4 = 0x%08x\n", mccr4);
 		pci_ppc_write_config32(0, 0, 0xfc, mccr4);
 
 		udelay(200);
@@ -519,13 +530,14 @@ mpc107_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
 		 * Set MEMGO bit
 		 */
 		mccr1 |= 0x80000;
-		printk_info("MCCR1 = 0x%08x\n", mccr1);
+		printk_debug("  MCCR1 = 0x%08x\n", mccr1);
 		pci_ppc_write_config32(0, 0, 0xf0, mccr1);
 
 		udelay(10000);
+		printk_debug("done.\n");
 	}
     
-	return address;
+	return mem_size;
 }
 
 static int
@@ -542,7 +554,7 @@ i2c_wait(unsigned timeout, int writing)
 		return -1;
 	}
 	if (writing && (x & MPC107_I2C_CSR_RXAK)) {
-		printk_info("No RXAK\n");
+		printk_debug("No RXAK\n");
 		/* generate stop */
 		writel(MPC107_I2C_CCR_MEN, MPC107_BASE + MPC107_I2CCR);
 		return -1;
@@ -695,7 +707,7 @@ i2c_fn mpc107_i2c_fn = {
  * Find dimm information.
  */
 void
-mpc107_probe_dimms(int no_dimms, sdram_dimm_info *dimms, sdram_bank_info * bank)
+mpc107_probe_dimms(int no_dimms, sdram_dimm_info *dimms, sdram_bank_info *bank)
 {
 	unsigned char data[256];
 	unsigned dimm;
@@ -721,7 +733,7 @@ mpc107_probe_dimms(int no_dimms, sdram_dimm_info *dimms, sdram_bank_info * bank)
 			data, DIMM_LENGTH);
 		
 		if (limit > 3) {
-			sdram_dimm_to_bank_info(data, dimms + dimm, 1);
+			sdram_dimm_to_bank_info(data, dimms + dimm);
 			memcpy(dimms[dimm].part_number, data + 73, 18);
 			dimms[dimm].part_number[18] = 0;
 			printk_debug("Part Number: %s\n", dimms[dimm].part_number);