intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES

This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.

Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.

BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.

Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Barnali Sarkar 2017-12-27 13:48:58 +05:30 committed by Subrata Banik
parent acc2a4819c
commit f43adf0b89
1 changed files with 2 additions and 6 deletions

View File

@ -135,14 +135,10 @@ static void post_cpus_init(void *unused)
if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
printk(BIOS_ERR, "MTRR programming failure\n");
/* Temporarily cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
fast_spi_cache_bios_region();
x86_mtrr_check();
}
/* Do CPU MP Init before FSP Silicon Init */
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_cpus, NULL);
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, post_cpus_init, NULL);
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL);