diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c
index a149e57fa9..2d59bd3adb 100644
--- a/src/soc/amd/cezanne/smihandler.c
+++ b/src/soc/amd/cezanne/smihandler.c
@@ -47,6 +47,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;
diff --git a/src/soc/amd/mendocino/smihandler.c b/src/soc/amd/mendocino/smihandler.c
index 9fda2f9c1a..de09dc3e5a 100644
--- a/src/soc/amd/mendocino/smihandler.c
+++ b/src/soc/amd/mendocino/smihandler.c
@@ -47,6 +47,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c
index 08f805bf76..b4cab2d717 100644
--- a/src/soc/amd/picasso/smihandler.c
+++ b/src/soc/amd/picasso/smihandler.c
@@ -45,6 +45,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;